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US4458336A
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Semiconductor memory circuit
Assignee: Fujitsu Ltd
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Filing: 1981-10-21
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Granted: 1984-07-03
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Expires: 2001-10-21
Abstract
Abstract A semiconductor memory circuit is disclosed, which includes: word lines, bit lines and memory cells at each cross point of the word lines and the bit lines. Each memory cell including a capacitor, having a first electrode and a second electrode, and a transfer-gate transistor connected in series with the capacitor at the first electrode thereof. The memory circuit also includes pre-charge circuits each charging one corresponding bit line to a predetermined pre-charge voltage level by using a memory power source and sense amplifiers each amplifying the voltage level developed at one corresponding bit line so as to have a high voltage level or a low voltage level in accordance with the charge stored in each corresponding capacitor. Additionally included are a first circuit which supplies the pre-charge voltage to the pre-charge circuit, the level of the pre-charge voltage is in the middle between the high voltage level and the low voltage level, and a second circuit which supplies a predetermined voltage to the capacitor at its second electrode. Preferably the predetermined voltage supplied from the second circuit is same as the voltage supplied from the first circuit.
Inventors
- 👤 Yoshihiro Takemae
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:35
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C11/409; G11C11/4094; G11C11/4099
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
226 words
A semiconductor memory circuit, comprising: a plurality of word lines; a plurality of bit line pairs; a plurality of memory cells, each one of the memory cells operatively connected at corresponding ones of cross points of the word lines and the bit lines, each memory cell comprising: a capacitor having a first electrode and a second electrode as a pair of electrodes; and a transfer-gate transistor operatively connected to the corresponding bit line and in series with the capacitor at the first electrode thereof; a plurality of pre-charge circuits, one of the pre-charge circuits operatively connected to each bit line pair, each charging the corresponding bit line pair to a predetermined pre-charge voltage level; amplifying means including a plurality of sense amplifiers, each one of the sense amplifiers operatively connected to each bit line pair, for amplifying the voltage level difference between the corresponding bit line pair to develop a high voltage level and a low voltage level in accordance with the charge stored in each corresponding capacitor; a circuit, operatively connected to the pre-charge circuits, for supplying the pre-charge voltage to the pre-charge circuits, the level of the pre-charge voltage being in the middle between the high voltage level and the low voltage level; and supply means, operatively connected to each capacitor, for supplying a predetermined voltage to each capacitor at the second electrode thereof.
Claim 2
Dependent Claim
226 words
A semiconductor memory circuit, comprising: a plurality of word lines; a plurality of bit line pairs; a plurality of memory cells, each one of the memory cells operatively connected at corresponding ones of cross points of the word lines and the bit lines, each memory cell comprising: a capacitor having a first electrode and a second electrode as a pair of electrodes; and a transfer-gate transistor operatively connected to the corresponding bit line and in series with the capacitor at the first electrode thereof; a plurality of pre-charge circuits, one of the pre-charge circuits operatively connected to each bit line pair, each charging the corresponding bit line pair to a predetermined pre-charge voltage level; amplifying means including a plurality of sense amplifiers, each one of the sense amplifiers operatively connected to each bit line pair, for amplifying the voltage level difference between the corresponding bit line pair to develop a high voltage level and a low voltage level in accordance with the charge stored in each corresponding capacitor; a circuit, operatively connected to the pre-charge circuits, for supplying the pre-charge voltage to the pre-charge circuits, the level of the pre-charge voltage being in the middle between the high voltage level and the low voltage level; and supply means, operatively connected to each capacitor, for supplying a predetermined voltage to each capacitor at the second electrode thereof.
Claim 3
Dependent Claim
56 words
A semiconductor memory circuit as set forth in claim 1, wherein said predetermined voltage supplied from said second circuit is the same as the pre-charge voltage supplied from said first circuit, the level of the pre-charge voltage is in the middle between the high voltage level and the low voltage level developed at the bit line.
Claim 4
Dependent Claim
21 words
A semiconductor memory circuit as set forth in claim 2, wherein both said first and second circuit comprise a voltage divider.
Claim 5
Dependent Claim
56 words
A semiconductor memory circuit as set forth in claim 3, wherein said semiconductor memory circuit has operatively connectable thereto first and second voltage levels, and wherein said high voltage level and low voltage level, developed at the bit line, are selected to be the levels of the first voltage level and the second voltage level, respectively.
Claim 6
Dependent Claim
28 words
A semiconductor memory circuit as set forth in claim 4, wherein said voltage divider divides a voltage difference between the first voltage level and the second voltage level.
Claim 7
Dependent Claim
49 words
A semiconductor memory circuit as set forth in claim 5, wherein said amplifying means further comprises dynamic pull-up circuits, one of the dynamic pull-up circuits operatively connected to each bit line to pull the voltage levels of the respective bit lines to the level of the first voltage level.
Claim 8
Dependent Claim
143 words
A semiconductor memory circuit as set forth in claim 6, wherein said semiconductor memory circuit is operatively connected to receive a clock pulse, and wherein said dynamic pull-up circuit comprises: an enhancement type transistor having a gate, and first and second electrodes; a depletion type transistor having a gate and first and second electrodes; and a capacitor having a first electrode and a second electrode which receives the clock pulse, the first electrodes of both said enhancement and depletion type transistors are operatively connected to one of the bit lines, the second electrode of the depletion type transistor, the gate of the enhancement type transistor and the first electrode of the capacitor are commonly connected together, and the gate of the depletion type transistor receives the second voltage level and the second electrode of the enhancement type transistor receives the first voltage level.
Claim 9
Dependent Claim
104 words
A semiconductor memory circuit, comprising: a memory cell; a first dynamic pull-up circuit operatively connected to said memory cell; a sense amplifier operatively connected to said memory cell; a second dynamic pull-up circuit operatively connected to said sense amplifier, one of said first and second dynamic pull-up circuits at a time performing a pull-up operation to generate a first voltage level; a pre-charging circuit operatively connected to said sense amplifier and said first and second dynamic pull-up circuits; and a voltage divider, operatively connected to said pre-charging circuit and said memory cell, for providing a second voltage level lower than said first voltage level.
Claim 10
Dependent Claim
104 words
A semiconductor memory circuit, comprising: a memory cell; a first dynamic pull-up circuit operatively connected to said memory cell; a sense amplifier operatively connected to said memory cell; a second dynamic pull-up circuit operatively connected to said sense amplifier, one of said first and second dynamic pull-up circuits at a time performing a pull-up operation to generate a first voltage level; a pre-charging circuit operatively connected to said sense amplifier and said first and second dynamic pull-up circuits; and a voltage divider, operatively connected to said pre-charging circuit and said memory cell, for providing a second voltage level lower than said first voltage level.
Claim 11
Dependent Claim
93 words
A semiconductor memory circuit as set forth in claim 8, wherein said semiconductor memory circuit has first and second reference voltages applied thereto and is operatively connectable to receive a clock signal, and wherein said first and second dynamic pull-up circuits each comprise: a first transistor operatively connected to said sense amplifier and the second reference voltage; a second transistor operatively connected to said sense amplifier, said first transistor and the first reference voltage; and a capacitor operatively connected to said first and second transistors and operatively connectable to receive the clock signal.
Claim 12
Dependent Claim
103 words
A semiconductor memory device as set forth in claim 9, wherein said pre-charging circuit comprises: a third transistor operatively connected to said sense amplifier and said voltage divider; a fourth transistor operatively connected to said third transistor, said sense amplifier and said voltage divider; a fifth transistor operatively connected to said third and fourth transistors, and wherein said voltage divider comprises: a first resistor operatively connected to the first reference voltage, said capacitor of said memory cell and said third and fourth transistors of said pre-charging circuit; and a second resistor operatively connected to the second reference voltage and to said first resistor.
Claim 13
Dependent Claim
56 words
A semiconductor memory device as set forth in claim 8, wherein said pre-charging circuit comprises: a first transistor operatively connected to said sense amplifier and said voltage divider; a second transistor operatively connected to said first transistor, said sense amplifier and said voltage divider; and a third transistor operatively connected to said first and second transistors.
Claim 14
Dependent Claim
33 words
A semiconductor memory device as set forth in claim 8, wherein said memory cell comprises: a first transistor operatively connected to said sense amplifier; and a capacitor operatively connected to said first transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-03 | 1988-01-02 | 1988-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-03 | 1992-01-02 | 1992-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-03 | 1996-01-02 | 1996-07-03 | $7700.00 | Window Closed / Lapsed |