US4458259A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Etched-source static induction transistor
Assignee: Verizon Laboratories Inc
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Filing: 1981-11-12
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Granted: 1984-07-03
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Expires: 2001-11-12
Abstract
Abstract A gate-source structure and fabrication method for a static induction transistor. The method and the device are embodied by the epitaxial layer of, for example, high resistivity p-type semiconductor material grown on an epitaxial layer of high resistivity n-type semiconductor material. A silicon dioxide layer with source and gate windows is formed on the p-type epitaxial layer. Source grooves are formed in the p-type epitaxial layer at source window locations and the grooves are diffused with n-type impurities to form a diffusion region which extends to connect with the n-type epitaxial layer. Source and gate electrodes are formed in the source and gate windows.
Inventors
- 👤 Adrian I. Cogan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:02
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/202
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
121 words
A gate-source structure for a static induction transistor comprising: a high resistivity epitaxial layer of one conductivity type; a high resistivity epitaxial layer of opposite conductivity type formed on said one-type epitaxial layer; a silicon dioxide layer formed on said opposite-type epitaxial layer; parallel source and gate windows in said silicon dioxide layer; source groove in said opposite-type epitaxial layer at the location of said source windows; diffused region of said one conductivity type extending from the surface of said grooves through said opposite-type epitaxial layer to form a channel to said one-type epitaxial layer; gate electrodes deposited on said opposite-type epitaxial layer at said gate window locations; and source electrode deposited on said diffused region at said source groove surface.
Claim 2
Dependent Claim
121 words
A gate-source structure for a static induction transistor comprising: a high resistivity epitaxial layer of one conductivity type; a high resistivity epitaxial layer of opposite conductivity type formed on said one-type epitaxial layer; a silicon dioxide layer formed on said opposite-type epitaxial layer; parallel source and gate windows in said silicon dioxide layer; source groove in said opposite-type epitaxial layer at the location of said source windows; diffused region of said one conductivity type extending from the surface of said grooves through said opposite-type epitaxial layer to form a channel to said one-type epitaxial layer; gate electrodes deposited on said opposite-type epitaxial layer at said gate window locations; and source electrode deposited on said diffused region at said source groove surface.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-03 | 1988-01-02 | 1988-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-03 | 1992-01-02 | 1992-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-03 | 1996-01-02 | 1996-07-03 | $7700.00 | Window Closed / Lapsed |