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US4458214A
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Fast sampling phase locked loop frequency synthesizer
Assignee: Bendix Corp
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Filing: 1981-09-28
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Granted: 1984-07-03
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Expires: 2001-09-28
Abstract
Abstract The output frequency of a phase locked loop frequency synthesizer is measured by a counter which counts whole output cycles and a timer providing a signal proportional to a fractional output cycle during a sampling period. The counter output is stored into a latch at each sampling period. Calculated frequency is generated by an accumulator which is incremented a selectable integer N at the completion of each sampling period. The accumulator output is divided into a first part relating to whole cycles and a second part relating to fractional cycles. An adder takes the difference of the latch stored number and the accumulator output first part. The resulting difference, with the accumulator output second part restored thereto, comprises a coarse error signal in digital form. The digital coarse error signal is converted to analog and applied as one input to a summer. A second input to the summer is provided by the timer signal after being scaled proportionately to N in a multiplying D/A converter. The summer output constitutes a refined error signal which is applied through a loop filter to regulate the output frequency of the phase locked voltage controlled oscillator.
Inventors
- 👤 Paul E. Lakomy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:11
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/1806; H03L7/08; H03L7/085; H03L7/091; H03L7/181
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
219 words
A phase locked loop frequency synthesizer comprising: oscillator means responsive to a refined error signal for generating an output frequency signal Nf r , where N is a positive integer and f r is a reference frequency; a source of a sampling signal Kf r where K is a positive integer; means for generating a first signal representing the number of whole cycles of said output frequency signal generated since a reference time zero; means responsive to said sampling signal for sampling said first signal at the Kf r rate; means responsive to said sampling signal for generating a second signal representing a number which is incremented by N stepwise at said Kf r rate; means for dividing said second signal by K to obtain a first part representing whole cycles of a computed frequency signal and a second part representing a computed fractional part of a cycle of said computed frequency signal; means combining the sampled first signal with said first and second parts of said second signal to generate a coarse error signal; means for generating a third signal representing a measured fractional portion of a cycle of said output frequency signal occurring during a period of said sampling signal; and, means combining said third signal and said coarse error signal to generate said refined error signal.
Claim 2
Dependent Claim
219 words
A phase locked loop frequency synthesizer comprising: oscillator means responsive to a refined error signal for generating an output frequency signal Nf r , where N is a positive integer and f r is a reference frequency; a source of a sampling signal Kf r where K is a positive integer; means for generating a first signal representing the number of whole cycles of said output frequency signal generated since a reference time zero; means responsive to said sampling signal for sampling said first signal at the Kf r rate; means responsive to said sampling signal for generating a second signal representing a number which is incremented by N stepwise at said Kf r rate; means for dividing said second signal by K to obtain a first part representing whole cycles of a computed frequency signal and a second part representing a computed fractional part of a cycle of said computed frequency signal; means combining the sampled first signal with said first and second parts of said second signal to generate a coarse error signal; means for generating a third signal representing a measured fractional portion of a cycle of said output frequency signal occurring during a period of said sampling signal; and, means combining said third signal and said coarse error signal to generate said refined error signal.
Claim 3
Dependent Claim
26 words
The phase locked loop frequency synthesizer of claim 1 wherein K is chosen to be of the form 2 m where m is a positive integer.
Claim 4
Dependent Claim
17 words
The phase locked loop frequency synthesizer of claim 2 including means for changing the value of N.
Claim 5
Dependent Claim
55 words
The phase locked loop frequency synthesizer of claim 2 wherein said combining means comprises: means for summing said third signal and said coarse error signal; a sample and hold circuit means for sampling and holding the output of said means for summing at said Kf r rate, the held sample being said refined error signal.
Claim 6
Dependent Claim
194 words
A fast sampling digital phase locked loop frequency synthesizer comprising: a voltage controlled oscillator responsive to a refined error signal for generating an output frequency signal Nf r , where N is a positive integer and f r is a reference frequency; a source of a sampling signal 2 m f r , where m is a positive integer; a digital counter for counting whole cycles of said output frequency signal to generate a first digital number; a digital accumulator for generating a second digital number which is incremented by N stepwise at said 2 m f r rate; means for taking the difference of said first and second digital numbers at said 2 m f r rate to thereby generate a third digital number having at least a part comprised of m bits representing a computed fractional part of a cycle of a computed frequency; means for generating a measured fractional cycle signal representing a measured fractional portion of a cycle of said output frequency signal occurring during a period of said sampling signal; and means combining said third digital number with the measured fractional cycle signal to generate said refined error signal.
Claim 7
Dependent Claim
194 words
A fast sampling digital phase locked loop frequency synthesizer comprising: a voltage controlled oscillator responsive to a refined error signal for generating an output frequency signal Nf r , where N is a positive integer and f r is a reference frequency; a source of a sampling signal 2 m f r , where m is a positive integer; a digital counter for counting whole cycles of said output frequency signal to generate a first digital number; a digital accumulator for generating a second digital number which is incremented by N stepwise at said 2 m f r rate; means for taking the difference of said first and second digital numbers at said 2 m f r rate to thereby generate a third digital number having at least a part comprised of m bits representing a computed fractional part of a cycle of a computed frequency; means for generating a measured fractional cycle signal representing a measured fractional portion of a cycle of said output frequency signal occurring during a period of said sampling signal; and means combining said third digital number with the measured fractional cycle signal to generate said refined error signal.
Claim 8
Dependent Claim
62 words
The fast sampling digital phase locked loop frequency synthesizer of claim 5 wherein said means for generating a measured fractional cycle signal comprises: a timer responsive to said sampling signal and said output frequency signal for generating a time signal; and, means for taking the product of said time signal and N, said product being proportional to said measured fractional cycle signal.
Claim 9
Dependent Claim
20 words
The fast sampling digital phase locked loop frequency synthesizer of claim 6 including means for changing the value of N.
Claim 10
Dependent Claim
21 words
The fast sampling digital phase locked loop frequency synthesizer of claim 7 wherein 2 m f r is a constant frequency.
References Cited (Backward Citations)
US3555446A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-03 | 1988-01-02 | 1988-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-03 | 1992-01-02 | 1992-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-03 | 1996-01-02 | 1996-07-03 | $7700.00 | Window Closed / Lapsed |