Patent US4458213A successfully refreshed from Google Patents.
US4458213A
Expired / Lapsed
US
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Constant quiescent current, class AB amplifier output stage
Assignee: Sony Corp
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Filing: 1982-12-13
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Granted: 1984-07-03
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Expires: 2002-12-13
Abstract
Abstract A circuit maintains the quiescent collector current of an output transistor amplifier constant by sensing the voltage developed across a resistor connected in series with the output transistor's collector and, using a differential amplifier, produces a first signal representative thereof which is sampled and held by a circuit controlled by a zero voltage crossing detector sensitive to the amplifier output voltage. The sampled and held signal is inverted and integrated with respect to an adjustable reference voltage to produce a second signal. The second signal controls the current passed by a transistor connected in a voltage divider network supplying the base bias voltage to the output transistor.
Inventors
- 👤 Ronald Quan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:14
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/30; H03F1/303
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
167 words
In combination with a transistor amplifier for receiving an input signal and producing a corresponding, amplified, output signal and having at least one output transistor, means for controlling the quiescent collector current of the output transistor, comprising differential amplifier means for sensing the output transistor's collector current and for producing a first signal proportional thereto, zero-crossing detector means supplied with the output signal, a sample and hold means supplied with the first signal and controlled by the zero-crossing detector means to sample and hold the first signal whenever the output signal is at zero voltage, means for supplying a reference signal, inverter/integrator means for inverting the sampled and held first signal and for producing a second signal which is representative of the integrated difference between the sampled and held first signal and the reference signal, and bias control means supplied with the second signal for supplying a bias voltage to the output transistor in response to the second signal whereby the quiescent collector current is maintained constant.
Claim 2
Dependent Claim
167 words
In combination with a transistor amplifier for receiving an input signal and producing a corresponding, amplified, output signal and having at least one output transistor, means for controlling the quiescent collector current of the output transistor, comprising differential amplifier means for sensing the output transistor's collector current and for producing a first signal proportional thereto, zero-crossing detector means supplied with the output signal, a sample and hold means supplied with the first signal and controlled by the zero-crossing detector means to sample and hold the first signal whenever the output signal is at zero voltage, means for supplying a reference signal, inverter/integrator means for inverting the sampled and held first signal and for producing a second signal which is representative of the integrated difference between the sampled and held first signal and the reference signal, and bias control means supplied with the second signal for supplying a bias voltage to the output transistor in response to the second signal whereby the quiescent collector current is maintained constant.
Claim 3
Dependent Claim
19 words
The combination as recited in claim 1 wherein the amplifier comprises a pair of output transistors in push-pull configuration.
Claim 4
Dependent Claim
49 words
The combination as recited in claim 1 wherein the bias control means comprises a voltage divider means including a resistor and a transistor having its collector and emitter leads connected in series with said resistor, and wherein the base lead of said transistor is supplied with said second signal.
References Cited (Backward Citations)
US4306109A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-03 | 1988-01-02 | 1988-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-03 | 1992-01-02 | 1992-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-03 | 1996-01-02 | 1996-07-03 | $7700.00 | Window Closed / Lapsed |