US4456980A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: NTT Inc
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Filing: 1982-03-15
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Granted: 1984-06-26
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Expires: 2002-03-15
Abstract
Abstract A semiconductor memory device comprises at least one word line, a plurality of bit lines extending across the word line, a data memory cell unit including a plurality of data memory cells connected between the word line and the bit lines for storing information, a plurality of first extra bit lines corresponding to first groups of the bit lines, each of which has k bit lines (k is an integer), and extending across the word line, a plurality of first extra memory cells connected between the word line and the first extra bit lines for storing first checking information with respect to the first groups of the bit lines, a plurality of second extra bit lines corresponding to second groups of the bit lines, each of which group has m bit lines (m is an integer), and extending across the word line, a plurality of second extra memory cells connected between the word line and the second extra bit lines for storing second checking information with respect to the second groups of the bit lines, an error detection circuit for comparing the information fed from the data memory cells with the contents of the first and second extra memory cells to detect errors, and a circuit responsive to an output from the error detection circuit for correcting the information fed from the data memory cells, the first extra bit lines being grouped correspondingly to the first groups of the bit lines, the second extra bit lines being grouped correspondingly to the second groups of the bit lines, each of the second groups of the second extra bit lines being composed of the first extra bit lines in each first group thereof.
Inventors
- 👤 Junzo Yamada
- 👤 Tsuneo Mano
- 👤 Junichi Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:01
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
284 words
A semiconductor memory device comprising: at least one word line; a plurality of bit lines extending across said word line; a data memory cell unit including a plurality of data memory cells connected between said word line and said bit lines for storing information; a plurality of first extra bit lines corresponding to first groups of the bit lines, each of which group has k bit lines (k is an integer), and extending across said word line; a plurality of first extra memory cells connected between said word line and said first extra bit lines for storing first checking information with respect to the first groups of the bit lines; a plurality of second extra bit lines corresponding to second groups of the bit lines, each of which group has m bit lines (m is an integer), and extending across said word line; a plurality of second extra memory cells connected between said word line and said second extra bit lines for storing second checking information with respect to the second groups of the bit lines; an error detection circuit for comparing the information fed from the data memory cells with the contents of said first and second extra memory cells to detect errors; a circuit responsive to an output from said error detection circuit for correcting the information fed from said data memory cells; and said first extra bit lines being grouped correspondingly to said first gorups of the bit lines, said second extra bit lines being gruped correspondingly to said second groups of the bit lines, each of the second groups of the second extra bit lines being composed of one of the first extra bit lines in each first grup thereof.
Claim 2
Dependent Claim
284 words
A semiconductor memory device comprising: at least one word line; a plurality of bit lines extending across said word line; a data memory cell unit including a plurality of data memory cells connected between said word line and said bit lines for storing information; a plurality of first extra bit lines corresponding to first groups of the bit lines, each of which group has k bit lines (k is an integer), and extending across said word line; a plurality of first extra memory cells connected between said word line and said first extra bit lines for storing first checking information with respect to the first groups of the bit lines; a plurality of second extra bit lines corresponding to second groups of the bit lines, each of which group has m bit lines (m is an integer), and extending across said word line; a plurality of second extra memory cells connected between said word line and said second extra bit lines for storing second checking information with respect to the second groups of the bit lines; an error detection circuit for comparing the information fed from the data memory cells with the contents of said first and second extra memory cells to detect errors; a circuit responsive to an output from said error detection circuit for correcting the information fed from said data memory cells; and said first extra bit lines being grouped correspondingly to said first gorups of the bit lines, said second extra bit lines being gruped correspondingly to said second groups of the bit lines, each of the second groups of the second extra bit lines being composed of one of the first extra bit lines in each first grup thereof.
Claim 3
Dependent Claim
50 words
A semiconductor memory device according to claim 1, wherein said first extra memory cells being capable of storing horizontal parity check bit information for said data memory cell unit, and said second extra memory cell being capable of storing vertical parity check bit information for said data memory cell unit.
Claim 4
Dependent Claim
44 words
A semiconductor memory device according to claim 1, further including horizontal and vertical parity check bit generators connected to said bit lines which are grouped differently for storing horizontal and vertical parity check bit information respectively into said first and second extra memory cells.
Claim 5
Dependent Claim
34 words
A semiconductor memory device according to claim 1, including a data input circuit for selectively supplying data from an exterior source and an output from said correcting cirucit to each of said bit lines.
Claim 6
Dependent Claim
92 words
A semiconductor memory device according to claim 1, wherein said error detection circuit comprises a horizontal parity checking circuit for comparing information from said data memory cells with horizontal parity check bit information from said first memory cells, and a vertical parity checking circuit for comparing information from said data memory cells with vertical parity check bit information from said second extra memory cells, the arrangement being that said correcting circuit corrects information from said data memory cells when outputs from said horizontal and vertical parity checking circuits agree with eac other.
Claim 7
Dependent Claim
127 words
A semiconductor memory device according to claim 5, wherein said correcting circuit comprises a plurality of first selectors for selecting data bit lines which constitute said second groups respectively from said first groups of the data bit lines and for connecting the selected data bit lines to said vertical parity checking ciruit, a second selector for selecting one group out of said first groups of the data bit lines, and third and fourth selectors for selecting first and second extra bit lines corresponding to said selected data bit lines from said plurality of first and second extra bit lines for said first and second extra memory cells and for connencting the selected first and second extra bit lines respectively to said horizontl and vertical parity checking circuits.
Claim 8
Dependent Claim
35 words
A semiconductor memory device according to claim 6, wherein said correcting circuit includes a fifth selector for successively selecting outputs from said second selector and for connecting the selected outputs to the error correcting circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-26 | 1987-12-26 | 1988-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-26 | 1991-12-26 | 1992-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-26 | 1995-12-26 | 1996-06-26 | $7700.00 | Window Closed / Lapsed |