US4455739A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process protection for individual device gates on large area MIS devices
Assignee: Texas Instruments Inc
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Filing: 1982-04-19
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Granted: 1984-06-26
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Expires: 2002-04-19
Abstract
Abstract Gates of individual devices on a slice are connected through a resistance to the device substrate, and through the same resistance to other device gates. This interconnection and high-resistance drain gives the gate protection from static charge buildup and subsequent catastrophic discharge which would result in a faulty device. This method protects each gate from the time of deposition to final device packaging.
Inventors
- 👤 Jaroslav Hynecek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:17
CPC Classifications
H; H10; H10W; H10W42/00; H10W42/60; Y; Y10; Y10S; Y10S438/00; Y10S438/91
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
68 words
A method for protecting individual device gates on a semiconductor slice during the device fabrication process, comprising: interconnecting the gates of a plurality of said individual devices on said slice; and coupling said interconnected gates to a reference voltage through a resistive element such that charge can flow to and from the gates prior to dicing the slice into individual devices; and dicing the slice into individual devices.
Claim 2
Independent Claim
68 words
A method for protecting individual device gates on a semiconductor slice during the device fabrication process, comprising: interconnecting the gates of a plurality of said individual devices on said slice; and coupling said interconnected gates to a reference voltage through a resistive element such that charge can flow to and from the gates prior to dicing the slice into individual devices; and dicing the slice into individual devices.
Claim 3
Independent Claim
100 words
A method for protecting individual device gates on a semiconductor slice during the device fabrication process comprising: interconnecting the gates of all said individual devices on said slice, each individual device having a border region, wherein said interconnection comprises a strip of material between the border region of individual devices, said border region of individual devices connected to the individual device gate through an individual resistive element, said border region, said resistive element, said gate, and said interconnecting strip all comprising the same material and deposited simultaneously; and coupling said interconnected gates to a reference voltage through said resistive element.
Claim 4
Independent Claim
100 words
A method for protecting individual device gates on a semiconductor slice during the device fabrication process comprising: interconnecting the gates of all said individual devices on said slice, each individual device having a border region, wherein said interconnection comprises a strip of material between the border region of individual devices, said border region of individual devices connected to the individual device gate through an individual resistive element, said border region, said resistive element, said gate, and said interconnecting strip all comprising the same material and deposited simultaneously; and coupling said interconnected gates to a reference voltage through said resistive element.
Claim 5
Dependent Claim
18 words
A method as in claim 1, wherein said resistive element is coupled to the substrate of said device.
Claim 6
Independent Claim
56 words
A method for protecting individual device gates on a semiconductor slice during the fabrication process comprising the step of interconnecting the gates of a plurality of individual devices on said slice through individual resistive elements of said individual devices wherein the resistive elements, gates and interconnection material between the gates are comprised of the same material.
Claim 7
Independent Claim
56 words
A method for protecting individual device gates on a semiconductor slice during the fabrication process comprising the step of interconnecting the gates of a plurality of individual devices on said slice through individual resistive elements of said individual devices wherein the resistive elements, gates and interconnection material between the gates are comprised of the same material.
Claim 8
Independent Claim
95 words
A method for protecting individual device gates on a semiconductor slice during the device fabrication process, comprising the step of interconnecting the gates of all individual devices, each device having a border region, on said slice through individual resistive elements on said individual devices wherein said interconnection comprises a strip of material between the border region of individual devices said border region of individual devices connected to the individual device gate through said resistive element, said border region, said resistive element, said gate and said interconnecting strip all comprising the same material and deposited simultaneously.
Claim 9
Independent Claim
95 words
A method for protecting individual device gates on a semiconductor slice during the device fabrication process, comprising the step of interconnecting the gates of all individual devices, each device having a border region, on said slice through individual resistive elements on said individual devices wherein said interconnection comprises a strip of material between the border region of individual devices said border region of individual devices connected to the individual device gate through said resistive element, said border region, said resistive element, said gate and said interconnecting strip all comprising the same material and deposited simultaneously.
Claim 10
Dependent Claim
13 words
The method according to claim 1 wherein the resistance value is 100 Kohms.
Claim 11
Dependent Claim
13 words
The method according to claim 4 wherein the resistance value is 100 Kohms.
Claim 12
Dependent Claim
14 words
The method according to claim 1 wherein a metalization step occurs after said coupling.
Claim 13
Dependent Claim
15 words
The method according to claim 1 wherein an ion implant occurs after said interconnecting step.
Claim 14
Dependent Claim
22 words
The method according to claim 1 wherein the interconnection material, gate material and resistive element are all comprised of the same material.
Claim 15
Dependent Claim
12 words
The method according to claim 1 wherein the reference voltage is ground.
Claim 16
Dependent Claim
19 words
The method according to claim 1 wherein all electrical connections between the gates and the reference voltage are ohmic.
Claim 17
Dependent Claim
14 words
The method according to claim 1 wherein the device is a metal-insulator-semiconductor type device.
Claim 18
Dependent Claim
31 words
The method according to claim 1 wherein the value of said resistive element is such that charge can flow through at a rate sufficient to prevent the damage to the device.
Claim 19
Dependent Claim
47 words
The method according to claim 1 wherein the resistive element remains connected to said device gates after the dicing step and further includes a contact for connecting the individual devices to a reference voltage through said resistive element which is an individual resistive element for each gate.
Claim 20
Dependent Claim
24 words
The method according to claim 1 further including connecting the resistive element to the device substrate prior to dicing the slice into individual devices.
Claim 21
Dependent Claim
17 words
The method according to claim 5 further comprising an ion implant step occuring after said interconnection step.
Claim 22
Dependent Claim
39 words
The method according to claim 4 wherein the resistive element remains connected to said individual device gates after the dicing step and further includes a contact for connecting the individual devices to a reference voltage through the resistive element.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-26 | 1987-12-26 | 1988-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-26 | 1991-12-26 | 1992-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-26 | 1995-12-26 | 1996-06-26 | $7700.00 | Window Closed / Lapsed |