Patent US4455622A successfully refreshed from Google Patents.
US4455622A
Expired / Lapsed
US
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Bit-oriented line adapter system
Assignee: Unisys Corp
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Filing: 1982-03-05
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Granted: 1984-06-19
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Expires: 2002-03-05
Abstract
Abstract A line adapter unit working in conjunction with a microprocessor which serves to handle data transmission using the bit oriented protocol mode. The microprocessor can select any one of a plurality of input-output circuit units which provide specific control of communications to/from remote data terminals or data sets. The microprocessor can select and control various components of the input-output circuit means such as regulating the timing means and setting up command structures for controlling the type, the direction, and the conversion of serial bit data. Likewise, each component of an input-output circuit unit may request service via an interrupt to the microprocessor and receive a command or response required for further operations. Each input-output circuit unit is provided with a dedicated memory area associated with a given data communications line. An automatic calling unit output register is also provided which can receive signals from the microprocessor which can be used for automatic dialing of the remote data sets.
Inventors
- 👤 Richard A. Loskorn
- 👤 Philip D. Biehl
- 👤 Robert D. Catiller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:31
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
163 words
In a line support processor for controlling data transfer operations using bit oriented protocol between a host computer and a remote data terminal wherein said line support processor includes a line adapter, a data link interface unit and a microprocessor, said microprocessor including program data in an internal PROM and external RAM storage means and having an I/O bus and output control registers providing control data to said line adapter, a bit oriented line adapter system comprising: (a) input/output circuit means connecting a data terminal to a first switching means; (b) first switching means, controlled by said microprocessor, for transferring data from said microprocessor to said input/output circuit means, or transferring data from said input/output circuit means to a multiplexor means; (c) multiplexor means, having an output to said I/O bus, for conveying data bytes from said input/output circuit means to said microprocessor; (d) memory means, connected to said I/O bus, for buffering data being transferred between said microprocessor and said data terminal.
Claim 2
Dependent Claim
163 words
In a line support processor for controlling data transfer operations using bit oriented protocol between a host computer and a remote data terminal wherein said line support processor includes a line adapter, a data link interface unit and a microprocessor, said microprocessor including program data in an internal PROM and external RAM storage means and having an I/O bus and output control registers providing control data to said line adapter, a bit oriented line adapter system comprising: (a) input/output circuit means connecting a data terminal to a first switching means; (b) first switching means, controlled by said microprocessor, for transferring data from said microprocessor to said input/output circuit means, or transferring data from said input/output circuit means to a multiplexor means; (c) multiplexor means, having an output to said I/O bus, for conveying data bytes from said input/output circuit means to said microprocessor; (d) memory means, connected to said I/O bus, for buffering data being transferred between said microprocessor and said data terminal.
Claim 3
Dependent Claim
52 words
The line adapter system of claim 1, wherein said input/output circuit means includes: (a) synchronous controller means, operatively commanded by signals from said microprocessor, for transmitting data to, or receiving data from, said data terminal; (b) timing means, operatively controlled by said microprocessor, for clocking of data, line-protocol-message-timing, for transmission and reception.
Claim 4
Dependent Claim
41 words
The line adapter of claim 2, wherein said timing means includes: (b1) first timing means for timing program-instruction operations in said synchronous controller means; (b2) second timing means for generating the baud rate of data transfer in said synchronous controller means.
Claim 5
Dependent Claim
51 words
The line adapter system of claim 2, wherein said synchronous controller means includes: (a) command register means, operating upon control signals received from said microprocessor, for activating transmitter or receiver operations, and for providing flag signals to frame each sequence of address data, control data, information data, and frame check data.
Claim 6
Dependent Claim
54 words
The line adapter system of claim 2, wherein said memory means includes: (d1) an address input bus to receive memory address data from said microprocessor; (d2) a memory output bus connected to said microprocessor for reading-out addressed data from said memory means; (d3) I/O bus connection means for placing data into said memory means.
Claim 7
Dependent Claim
207 words
In a line support processor for controlling data transfer operations using bit oriented protocol between a host computer and a remote data terminal wherein said line support processor includes a line adapter, a data link interface unit and a microprocessor, said microprocessor including program data in an internal PROM and external RAM storage means and having an I/O bus and output control registers providing control data to said line adapter, a bit oriented line adapter system comprising: (a) a plurality of input/output circuit means, each of which connects a separate data terminal to a first switching means; (b) first switching means, controlled by said microprocessor, for transferring data from said microprocessor, to a selected one of said plurality of input/output circuit means or for transferring data from a selected one of said input/output circuit means to a multiplexor means; (c) multiplexor means, receiving data from said first switching means and receiving control signals from said plurality of input/output means, for transferring data from a selected one of said input/output circuit means to an I/O bus; (d) an I/O bus connecting the output of said multiplexor means to a memory means and to said microprocessor; (e) memory means connected to said I/O bus for buffering data being transferred.
Claim 8
Dependent Claim
207 words
In a line support processor for controlling data transfer operations using bit oriented protocol between a host computer and a remote data terminal wherein said line support processor includes a line adapter, a data link interface unit and a microprocessor, said microprocessor including program data in an internal PROM and external RAM storage means and having an I/O bus and output control registers providing control data to said line adapter, a bit oriented line adapter system comprising: (a) a plurality of input/output circuit means, each of which connects a separate data terminal to a first switching means; (b) first switching means, controlled by said microprocessor, for transferring data from said microprocessor, to a selected one of said plurality of input/output circuit means or for transferring data from a selected one of said input/output circuit means to a multiplexor means; (c) multiplexor means, receiving data from said first switching means and receiving control signals from said plurality of input/output means, for transferring data from a selected one of said input/output circuit means to an I/O bus; (d) an I/O bus connecting the output of said multiplexor means to a memory means and to said microprocessor; (e) memory means connected to said I/O bus for buffering data being transferred.
Claim 9
Dependent Claim
58 words
The line adapter system of claim 6, wherein each of said input/output circuit means includes: (a) synchronous controller means, operatively commanded by signals from said microprocessor, for transmitting data to, or receiving data from said data terminal or said first switching means; (b) timing means, controlled by signals from said microprocessor, for clocking of data transmission and reception.
Claim 10
Dependent Claim
23 words
The line adapter system of claim 7, wherein each of said input/output circuit means includes: (a) means to request service from said microprocessor.
Claim 11
Dependent Claim
36 words
The system of claim 8, wherein said means to request service includes: (a) an interrupt register, in said synchronous controller, which is settable by said synchronous controller or said timing means, to indicate need for service.
Claim 12
Dependent Claim
39 words
The system of claim 9, wherein said microprocessor includes: (a) means for identifying which line adapter is requesting service; (b) means to read each interrupt register of each input/output circuit means to determine which input/output circuit means requires service.
Claim 13
Dependent Claim
40 words
The line adapter system of claim 7, wherein said input/output circuit means includes: (a) means to address and write control signals from said microprocessor into said synchronous controller; (b) means to address and write control signals into said timing means.
Claim 14
Dependent Claim
35 words
The line adapter system of claim 7, which includes: (a) automatic calling unit output register means connected to said output register of said microprocessor for receiving dialing signal data for operating an automatic calling unit.
Claim 15
Dependent Claim
32 words
The system of claim 10, wherein said means to read includes: (a) means to determine whether a selected input/output circuit means requires service to its synchronous controller or to its timing means.
References Cited (Backward Citations)
US4343461A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-19 | 1987-12-19 | 1988-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-19 | 1991-12-19 | 1992-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-19 | 1995-12-19 | 1996-06-19 | $7700.00 | Window Closed / Lapsed |