Patent US4455568A successfully refreshed from Google Patents.
US4455568A
Expired / Lapsed
US
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Insulation process for integrated circuits
Assignee: American Microsystems Holding Corp
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Filing: 1981-08-27
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Granted: 1984-06-19
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Expires: 2001-08-27
Abstract
Abstract Capacitors or dual layer metalization interconnects are formed in an integrated circuit utilizing two layers of polycrystalline silicon (22, 24) separated by a thin insulation region (23). The insulation region formed between the two polycrystalline silicon regions has substantially fewer defects than the insulation regions used in prior art techniques due to the use of a unique process wherein the polycrystalline silicon layer (24) overlying the insulation layer (23) protects the insulation layer from attack during subsequent processing. An improved dielectric strength is provided by forming the insulation region (23) utilizing composite layers of silicon oxide (23a, 23c) and silicon nitride (23b).
Inventors
- 👤 Philip Shiota
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:55
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; Y; Y10; Y10S; Y10S148/00; Y10S148/014
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
103 words
A capacitor for use in an integrated circuit comprising: a first insulation layer formed on a semiconductor substrate; a first polycrystalline silicon region formed on said insulating layer; a second insulation layer formed on the surface of said first polycrystalline silicon region; said second insulation layer comprising a first layer of silicon dioxide, a layer of silicon nitride located on said first layer of silicon oxide, and a second layer of silicon dioxide located on said layer of silicon nitride; and a second polycrystalline silicon region formed on said second insulation layer and located above and insulated from said first polycrystalline silicon region.
Claim 2
Dependent Claim
103 words
A capacitor for use in an integrated circuit comprising: a first insulation layer formed on a semiconductor substrate; a first polycrystalline silicon region formed on said insulating layer; a second insulation layer formed on the surface of said first polycrystalline silicon region; said second insulation layer comprising a first layer of silicon dioxide, a layer of silicon nitride located on said first layer of silicon oxide, and a second layer of silicon dioxide located on said layer of silicon nitride; and a second polycrystalline silicon region formed on said second insulation layer and located above and insulated from said first polycrystalline silicon region.
Claim 3
Dependent Claim
28 words
Structure as in claim 1 wherein one or both of said first and said second polycrystalline silicon regions are doped with a selected dopant, thereby increasing their conductivity.
Claim 4
Dependent Claim
10 words
Structure as in claim 2 wherein said dopant is phosphorus.
Claim 5
Dependent Claim
27 words
Structure as in claims 1 or 2 wherein said first insulation layer comprises material selected from the group of materials consisting of silicon dioxide and silicon nitride.
Claim 6
Dependent Claim
31 words
Structure as in claim 1 wherein said layers of silicon dioxide have a thickness of approximately 150 angstroms and said layer of silicon nitride has a thickness of approximately 300 angstroms.
Claim 7
Dependent Claim
109 words
An interconnection structure for use in an integrated circuit comprising: a first insulation region formed on a semiconductor substrate; a first polycrystalline silicon region formed on said first insulation region; a second insulation region formed on the surface of said substrate and covering said first polycrystalline silicon region; said second insulation region comprising a first layer of silicon dioxide, a layer of silicon nitride located on said first layer of silicon dioxide, and a second layer of silicon dioxide located on said layer of silicon nitride; and a second polycrystalline silicon region formed on said second insulating region and located above and insulated from said first polycrystalline silicon region.
Claim 8
Dependent Claim
109 words
An interconnection structure for use in an integrated circuit comprising: a first insulation region formed on a semiconductor substrate; a first polycrystalline silicon region formed on said first insulation region; a second insulation region formed on the surface of said substrate and covering said first polycrystalline silicon region; said second insulation region comprising a first layer of silicon dioxide, a layer of silicon nitride located on said first layer of silicon dioxide, and a second layer of silicon dioxide located on said layer of silicon nitride; and a second polycrystalline silicon region formed on said second insulating region and located above and insulated from said first polycrystalline silicon region.
Claim 9
Dependent Claim
24 words
Structure as in claim 6 wherein said first and said second polycrystalline silicon regions are doped with a selected dopant, thereby increasing their conductivity.
Claim 10
Dependent Claim
10 words
Structure as in claim 7 wherein said dopant is phosphorus.
Claim 11
Dependent Claim
31 words
Structure as in claim 6 wherein said layers of silicon dioxide have a thickness of approximately 400 angstroms and said layer of silicon nitride has a thickness of approximately 2,000 angstroms.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-19 | 1987-12-19 | 1988-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-19 | 1991-12-19 | 1992-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-19 | 1995-12-19 | 1996-06-19 | $7700.00 | Window Closed / Lapsed |