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US4454523A
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High voltage field effect transistor
Assignee: Vishay Siliconix Inc
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Filing: 1981-03-30
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Granted: 1984-06-12
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Expires: 2001-03-30
Abstract
Abstract A high voltage field effect transistor includes a source region in a first major surface of a semiconductor body and a drain region in a second major surface of the semiconductor body. A first gate region is formed in the first major surface and is surrounded by the source regions. A second gate region surrounds the source region and includes a buried region extending into the semiconductor body between the source and drain regions. The buried gate structure can be fabricated by epitaxial grown over diffused regions in a semiconductor substrate, or alternatively ion implantation can be employed to form the buried gate regions.
Inventors
- 👤 Lorimer K. Hill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:02
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/87; H10D30/871; H10D30/83; H10D30/831
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
161 words
A high voltage field effect transistor comprising: a semiconductor body of a first conductivity type and and having first and second major parallel surfaces, a drain region of said first conductivity type in said first major surface, a source region of said first conductivity type in said second major surface, a first gate region of opposite conductivity type in said second major surface and surrounded by said source region, said first gate region comprising a Schottky barrier region, a second gate region of said opposite conductivity type in said second major surface and surrounding said source region, said second gate region extending into said semiconductor body between said source region and said drain region and thereby defining a current path between said source and drain regions which lies between said second gate region and said first gate region, a first contact to said drain region, and a second contact to said source region and to said first and second gate regions.
Claim 2
Dependent Claim
161 words
A high voltage field effect transistor comprising: a semiconductor body of a first conductivity type and and having first and second major parallel surfaces, a drain region of said first conductivity type in said first major surface, a source region of said first conductivity type in said second major surface, a first gate region of opposite conductivity type in said second major surface and surrounded by said source region, said first gate region comprising a Schottky barrier region, a second gate region of said opposite conductivity type in said second major surface and surrounding said source region, said second gate region extending into said semiconductor body between said source region and said drain region and thereby defining a current path between said source and drain regions which lies between said second gate region and said first gate region, a first contact to said drain region, and a second contact to said source region and to said first and second gate regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-12 | 1987-12-12 | 1988-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-12 | 1991-12-12 | 1992-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-12 | 1995-12-12 | 1996-06-12 | $7700.00 | Window Closed / Lapsed |