Patent US4453260A successfully refreshed from Google Patents.
US4453260A
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Synchronizing circuit for detecting and interpolating sync signals contained in digital signal
Assignee: Toshiba Corp
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Filing: 1982-09-27
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Granted: 1984-06-05
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Expires: 2002-09-27
Abstract
Abstract A synchronous circuit comprises a sync signal detecting circuit connected to receive a digital signal with a plurality of frames each consisting of N bits and containing a frame sync signal to detect a sync signal in each frame, and a sync protecting circuit for producing a sync control signal synchronized with the detection of the sync signals and interpolating the sync control signal every frame when the sync signal is not detected. The sync protecting circuit has a counter for counting the number of frames in which the sync signals are not detected. A circuit is provided to quickly synchronize the sync protecting circuit with the detection of the sync signal by the sync signal detecting circuit when noise is produced by the sync signal detecting circuit and then a sync signal is detected after a given value has been counted by the counter.
Inventors
- 👤 Jun Inagawa
- 👤 Masahide Nagumo
- 👤 Tadashi Kojima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:40
CPC Classifications
G; G11; G11B; G11B5/00; G11B5/02; G11B5/09; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/10527; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
515 words
A synchronizing circuit comprising: frame sync signal detecting circuit means connected to receive clock pulses and a digital input signal having a plurality of frames each consisting of N bits and having a frame sync signal for detecting the frame sync signal to produce a sync detect output signal; first counting means counting clock pulses and connected to receive an output signal of said frame sync signal detecting circuit means for producing an output signal synchronized with the output signal of said sync signal detecting circuit means, said first counting means being so arranged to be cleared by the output signal of said sync signal detecting circuit means and to provide an output signal each time N clock pulses are counted even if said sync signal detecting circuit means fails to detect the frame sync signal; first window generating means responsive to said first counting means for generating a window output signal at intervals at which said sync signal detecting circuit means detects the sync signals; second counting means for counting said window output signal of said first window generating means, said second counting means being cleared by each output signal of said sync signal detecting circuit means when said first counting means is synchronized with said sync signal detecting circuit means, and having its output state changed from a first state to a second state when said second counting means counts a given number of window output signals of said first window generating means when said sync signal detecting circuit means fails to detect the sync signals; a first gate circuit connected between said sync signal detecting circuit means and said first and second counting means for, when enabled, supplying an output signal of said sync signal detecting circuit means to said first and second counting means to clear said first and second counting means; a second gate circuit connected to receive said output signal of said sync signal detecting circuit means, said second gate circuit being enabled by an output signal of said second counting means when said second counting means is in said second output state; third counting means for counting the clock pulses to provide an output signal each time said third counting means counts N clock pulses, said third counting means being cleared by an output signal of said first and second gate circuits; a second window generating means connected to said third counting means for forming a window output signal at time intervals taken for said third counting means to count approximately N clock pulses; and means responsive to said second counting means for selectively coupling one of the output signals of said first and second window generating means to said first gate circuit to enable said first gate circuit, such that the window output signal of said first window generating means is applied to said first gate circuit when said second counting means is in said first output state and the window output signal of said second window generating means is applied to said first gate circuit when said second counting means is in said second output state.
Claim 2
Dependent Claim
515 words
A synchronizing circuit comprising: frame sync signal detecting circuit means connected to receive clock pulses and a digital input signal having a plurality of frames each consisting of N bits and having a frame sync signal for detecting the frame sync signal to produce a sync detect output signal; first counting means counting clock pulses and connected to receive an output signal of said frame sync signal detecting circuit means for producing an output signal synchronized with the output signal of said sync signal detecting circuit means, said first counting means being so arranged to be cleared by the output signal of said sync signal detecting circuit means and to provide an output signal each time N clock pulses are counted even if said sync signal detecting circuit means fails to detect the frame sync signal; first window generating means responsive to said first counting means for generating a window output signal at intervals at which said sync signal detecting circuit means detects the sync signals; second counting means for counting said window output signal of said first window generating means, said second counting means being cleared by each output signal of said sync signal detecting circuit means when said first counting means is synchronized with said sync signal detecting circuit means, and having its output state changed from a first state to a second state when said second counting means counts a given number of window output signals of said first window generating means when said sync signal detecting circuit means fails to detect the sync signals; a first gate circuit connected between said sync signal detecting circuit means and said first and second counting means for, when enabled, supplying an output signal of said sync signal detecting circuit means to said first and second counting means to clear said first and second counting means; a second gate circuit connected to receive said output signal of said sync signal detecting circuit means, said second gate circuit being enabled by an output signal of said second counting means when said second counting means is in said second output state; third counting means for counting the clock pulses to provide an output signal each time said third counting means counts N clock pulses, said third counting means being cleared by an output signal of said first and second gate circuits; a second window generating means connected to said third counting means for forming a window output signal at time intervals taken for said third counting means to count approximately N clock pulses; and means responsive to said second counting means for selectively coupling one of the output signals of said first and second window generating means to said first gate circuit to enable said first gate circuit, such that the window output signal of said first window generating means is applied to said first gate circuit when said second counting means is in said first output state and the window output signal of said second window generating means is applied to said first gate circuit when said second counting means is in said second output state.
Claim 3
Dependent Claim
429 words
A synchronizing circuit comprising: frame sync signal detecting circuit means connected to receive clock pulses and a digital input signal having a plurality of frames each consisting of N bits and having a frame sync signal for detecting the frame sync signal to produce a sync detect output signal; first counting means counting the clock pulses and connected to receive an output signal of said frame sync signal detecting circuit means for producing an output signal synchronized with the output signal of said sync signal detecting circuit means, said first counting means being so arranged to be cleared by the output signal of said sync signal detecting circuit means and to provide an output signal each time N clock pulses are counted even if said sync signal detecting circuit means fails to detect the frame sync signal; window generating means responsive to said first counting means for generating a window output signal at intervals at which said sync signal detecting circuit means detects the sync signals; second counting means for counting the window output signal of said window generating means, said second counting means being cleared by each output signal of said sync signal detecting circuit means when said first counting means is synchronized with said sync signal detecting circuit means, and having its output state changed from a first state to a second state when said second counting means counts a given number of window output signals of said first window generating means when said sync signal detecting circuit means fails to detect the sync signals; a first gate circuit connected between said sync signal detecting circuit means and said first counting means for, when enabled, supplying an output signal of said sync signal detecting circuit means to said first counting means to clear said first counting means; a second gate circuit connected between said sync signal detecting circuit means and said second counting means, said second gate circuit being enabled by the window output signal of said window generating means to apply an output signal of said sync signal detecting circuit means to said second counting means to clear said second counting means; and means responsive to said second counting means to supply the window output signal of said window generating means to said first gate circuit when said second counting means is in said first output state to enable said first gate circuit each time the window output signal is produced, and to enable said first gate circuit until said second counting means is cleared when said second counting means is in said second output state.
Claim 4
Dependent Claim
429 words
A synchronizing circuit comprising: frame sync signal detecting circuit means connected to receive clock pulses and a digital input signal having a plurality of frames each consisting of N bits and having a frame sync signal for detecting the frame sync signal to produce a sync detect output signal; first counting means counting the clock pulses and connected to receive an output signal of said frame sync signal detecting circuit means for producing an output signal synchronized with the output signal of said sync signal detecting circuit means, said first counting means being so arranged to be cleared by the output signal of said sync signal detecting circuit means and to provide an output signal each time N clock pulses are counted even if said sync signal detecting circuit means fails to detect the frame sync signal; window generating means responsive to said first counting means for generating a window output signal at intervals at which said sync signal detecting circuit means detects the sync signals; second counting means for counting the window output signal of said window generating means, said second counting means being cleared by each output signal of said sync signal detecting circuit means when said first counting means is synchronized with said sync signal detecting circuit means, and having its output state changed from a first state to a second state when said second counting means counts a given number of window output signals of said first window generating means when said sync signal detecting circuit means fails to detect the sync signals; a first gate circuit connected between said sync signal detecting circuit means and said first counting means for, when enabled, supplying an output signal of said sync signal detecting circuit means to said first counting means to clear said first counting means; a second gate circuit connected between said sync signal detecting circuit means and said second counting means, said second gate circuit being enabled by the window output signal of said window generating means to apply an output signal of said sync signal detecting circuit means to said second counting means to clear said second counting means; and means responsive to said second counting means to supply the window output signal of said window generating means to said first gate circuit when said second counting means is in said first output state to enable said first gate circuit each time the window output signal is produced, and to enable said first gate circuit until said second counting means is cleared when said second counting means is in said second output state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-05 | 1987-12-05 | 1988-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-05 | 1991-12-05 | 1992-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-05 | 1995-12-05 | 1996-06-05 | $7700.00 | Window Closed / Lapsed |