Pull-up circuit for a memory

Claim 2

A memory circuit comprising: a conductor; a plurality of memory cells, each memory cell coupled to said conductor; enabling means for enabling one of said memory cells; a diode-connected transistor coupled between said conductor and a common node; a pull-up transistor having a control electrode coupled to a pull-up signal, a first electrode coupled to the common node, and a second electrode coupled to a first power supply terminal; and pull-up means for providing the pull-up signal at a first predetermined voltage level when a control signal is at a first logic state, and for providing the pull-up signal at a second predetermined voltage level when the control signal is at a second logic state.

Claim 3

A column pull-up circuit comprising: first and second bit sense-lines; a plurality of memory cells, each memory cell coupled to both bit sense lines; row decoder means for enabling one of said memory cells in response to a row address signal; a first diode-connected transistor coupled between the first bit sense line and a common node; a second diode-connected transistor coupled between the second bit sense line and the common node; a pull-up transistor having a control electrode coupled to a pull-up node, a first electrode coupled to the common node, and a second electrode coupled to a power supply terminal; and pull-up means for providing a pull-up signal at a first voltage level to the pull-up node when a control signal is at a first logic state, and for providing the pull-up signal at a voltage level higher than said first voltage level when the control signal is at a second logic state.

Claim 4

A column pull-up circuit comprising: first and second bit sense-lines; a plurality of memory cells, each memory cell coupled to both bit sense lines; row decoder means for enabling one of said memory cells in response to a row address signal; a first diode-connected transistor coupled between the first bit sense line and a common node; a second diode-connected transistor coupled between the second bit sense line and the common node; a pull-up transistor having a control electrode coupled to a pull-up node, a first electrode coupled to the common node, and a second electrode coupled to a power supply terminal; and pull-up means for providing a pull-up signal at a first voltage level to the pull-up node when a control signal is at a first logic state, and for providing the pull-up signal at a voltage level higher than said first voltage level when the control signal is at a second logic state.

Claim 5

The memory circuit of claim 1 or 2 wherein the pull-up transistor is a natural transistor.

Claim 6

The memory circuit of claim 3 wherein the pull-up means comprises: a first transistor having a first electrode coupled to a second power supply terminal, a gate coupled to a complement of the control signal, and a second electrode coupled to an output node which is where the pull-up signal is provided; a second transistor having a control electrode and a first electrode coupled to the first power supply terminal, and a second electrode coupled to the output node; and a third transistor having a control electrode coupled to the control signal, a first electrode coupled to the output node, and a second electrode coupled to the first power supply terminal.

Claim 7

The memory circuit of claim 4 wherein the first transistor is an enhancement transistor, the second transistor is a natural transistor, and the third transistor is a depletion transistor.

Claim 8

A memory circuit comprising: a column conductor; a plurality of memory cells, each memory cell coupled to said column conductor; a diode-connected transistor coupled between the column conductor and a supply node; a pull-up transistor coupled between the supply node and a first power supply terminal; a bit sense common line; a coupling transistor having a first current electrode coupled to the bit sense common line, a second current electrode coupled to the column conductor, and a control electrode for receiving a decoder signal; and a column decoder having an output for providing the decoder signal to the control electrode of the coupling transistor in response to a predetermined address and a chip enable signal, wherein said column decoder has a chip enable transistor which is coupled between the output and the first power supply terminal and which is activated in response to the chip enable signal for enabling the column decoder to provide the decoder signal in response to the predetermined address.

Claim 9

A memory circuit comprising: a column conductor; a plurality of memory cells, each memory cell coupled to said column conductor; a diode-connected transistor coupled between the column conductor and a supply node; a pull-up transistor coupled between the supply node and a first power supply terminal; a bit sense common line; a coupling transistor having a first current electrode coupled to the bit sense common line, a second current electrode coupled to the column conductor, and a control electrode for receiving a decoder signal; and a column decoder having an output for providing the decoder signal to the control electrode of the coupling transistor in response to a predetermined address and a chip enable signal, wherein said column decoder has a chip enable transistor which is coupled between the output and the first power supply terminal and which is activated in response to the chip enable signal for enabling the column decoder to provide the decoder signal in response to the predetermined address.

Claim 10

The memory circuit of claim 6 further comprising: pull-up means for providing a pull-up signal at a first predetermined voltage level when a control signal is at a first logic state, and for providing the pull-up signal at a second predetermined voltage level when the control signal is at a second logic state; and wherein the pull-up transistor has a first current electrode coupled to the supply node, a second current electrode coupled to the first power supply terminal, and a control electrode for receiving the pull-up signal.

Claim 11

The memory circuit of claim 7 wherein the pull-up means comprises: a first transistor having a first electrode coupled to a second power supply terminal, a gate coupled to a complement of the control signal, and a second electrode coupled to an output node for providing the pull-up signal to the control electrode of the pull-up transistor; a second transistor having a control electrode and a first electrode coupled to the first power supply terminal, and a second electrode coupled to the output node; and a third transistor having a control electrode coupled to the control signal, a first electrode coupled to the output node, and a second electrode coupled to the first power supply terminal.

Claim 12

The memory circuit of claim 6 wherein the coupling and diode-connected transistors are enhancement transistors and the chip enable and pull-up transistors are natural transistors.