Method and apparatus for decoding binary data

Claim 1

A method of converting input data bit signals representative of binary data in one form entering an apparatus at a first fixed rate to output bit signals representative of the same data in another form exiting said apparatus at a second fixed rate according to a code, wherein according to said code there are more bit signals of the data in said one form than the bit signals of the same data in said another form, said method comprising: inputting a stream of known input bit signals into a register means of said apparatus; decoding said known input bit signals into output bit signals and storing them in an output means; comparing the decoded output bit signals to anticipated output bit signals that correspond to the binary data of the known input bit signals according to said code; selecting a predetermined delay to be inserted in the path from said register means to said output means such that the decoded output bit signals are in phase with the anticipated output bit signals, and then applying the input data bit signals to said register means whereby the inserted delay will then cause properly decoded output data bit signals to be stored in said output means.

Claim 2

A method of converting input data bit signals representative of binary data in one form entering an apparatus at a first fixed rate to output bit signals representative of the same data in another form exiting said apparatus at a second fixed rate according to a code, wherein according to said code there are more bit signals of the data in said one form than the bit signals of the same data in said another form, said method comprising: inputting a stream of known input bit signals into a register means of said apparatus; decoding said known input bit signals into output bit signals and storing them in an output means; comparing the decoded output bit signals to anticipated output bit signals that correspond to the binary data of the known input bit signals according to said code; selecting a predetermined delay to be inserted in the path from said register means to said output means such that the decoded output bit signals are in phase with the anticipated output bit signals, and then applying the input data bit signals to said register means whereby the inserted delay will then cause properly decoded output data bit signals to be stored in said output means.

Claim 5

An apparatus for converting input data bit signals representative of binary data in one form entering said apparatus at a first fixed rate to output data bit signals representative of the same data in another form exiting said apparatus at a second fixed rate according to a code, wherein according to said code there are more bit signals of the data in said one form than the bit signals of the same data in said another form, said apparatus comprising: input register means; means for applying said input data bit signals to said input shift register; means for applying a stream of known input bit signals to said input register means prior to the application thereto of said input data bit signals; output storage means; conversion means coupled to said input shift register means, said conversion means including decoding means, delay means, and switching means for causing one of a plurality of possible decoded signals decoded in accordance with said code to be stored in said output storage means; said delay means providing different predetermined delays for said plurality of possible decoded signals relative to one another so that said decoded signals respectively correspond to the different possible phase relationships which may be applied to said output storage means as a result of the decoding of input bit signals in accordance with said code; and logic means responsive to the decoded known input bit signals of said stream for determining the correct phase relationship to be provided for said input bit signals and for causing said switching means to select the correct corresponding one of said possible decoded signals to be applied to said output storage means.

Claim 6

An apparatus for converting input data bit signals representative of binary data in one form entering said apparatus at a first fixed rate to output data bit signals representative of the same data in another form exiting said apparatus at a second fixed rate according to a code, wherein according to said code there are more bit signals of the data in said one form than the bit signals of the same data in said another form, said apparatus comprising: input register means; means for applying said input data bit signals to said input shift register; means for applying a stream of known input bit signals to said input register means prior to the application thereto of said input data bit signals; output storage means; conversion means coupled to said input shift register means, said conversion means including decoding means, delay means, and switching means for causing one of a plurality of possible decoded signals decoded in accordance with said code to be stored in said output storage means; said delay means providing different predetermined delays for said plurality of possible decoded signals relative to one another so that said decoded signals respectively correspond to the different possible phase relationships which may be applied to said output storage means as a result of the decoding of input bit signals in accordance with said code; and logic means responsive to the decoded known input bit signals of said stream for determining the correct phase relationship to be provided for said input bit signals and for causing said switching means to select the correct corresponding one of said possible decoded signals to be applied to said output storage means.