Control circuit for liquid chromatograph

Claim 2

A circuit for producing a plurality of control signals comprising: means for producing a selected number of pulses during a given time period; a plurality of counters each settable to a given value prior to the start of said time period, the sum of the values set into said counters being less than or equal in number of said selectable number of pulses; means to selectively apply said pulses to one of said counters at a time to cause that counter to count down to zero and thereafter apply pulses to another said counter causing it to count down, said selective pulse applying means being operative to count all said counters to zero during said given period in a prescribed sequence; means responsive to all but one of said counters as each said counter is counted down to produce a unique control signal indicative of a particular one of said counters being counted down; and means responsive to said one remaining counter to produce another unique control signal whenever said one counter is not zero or when all said counters are zero.

Claim 3

The circuit of claim 1 wherein said selected number of pulses is a power of 10.

Claim 4

The circuit of claim 1 wherein said selected number of pulses is 1000.

Claim 5

The circuit of claim 1 wherein each said counter is a count down counter including an output signal indicative of the fact that value stored therein is not zero.

Claim 6

The circuit of claim 1 wherein said means for producing a selected number of pulses includes: a first pulse counter responsive to pulses at one rate for counting them during said time period; means to store the count of said first said pulse counter during the next cycle; and a second pulse counter means responsive to pulses at a second rate greater than said first rate and for producing a pulse at its output for every N pulses at said second rate where N is the number stored in said means to store.

Claim 7

The circuit of claim 1 wherein each control signal is coupled to a valve for controlling the flow of fluid therethrough.

Claim 8

A circuit for dividing a time period, which is gradually changeable in length, into a fixed number of sub-intervals comprising, in combination: means defining the time period to be subdivided; a source of pulses at a first pulse rate; means responsive to said source of pulses to produce pulses at a second pulse rate which is equal to said first pulse rate divided by M; first counter means responsive to said pulses at said second pulse rate and also responsive to said means defining a time period to be subdivided, said first counter means being operative to count the number of pulses at said second pulse rate occurring during said time period to be subdivided; latch means to store the count stored in said first counter means at the conclusion of a time period; a second counter means, responsive to said latch and to said pulses at said first pulse rate during the next time period to produce a pulse at its output for every N pulses input thereto at said first rate where N is the number stored in said latch means, said second counter producing M pulses at its output during the period to be subdivided.

Claim 9

A circuit for dividing a time period, which is gradually changeable in length, into a fixed number of sub-intervals comprising, in combination: means defining the time period to be subdivided; a source of pulses at a first pulse rate; means responsive to said source of pulses to produce pulses at a second pulse rate which is equal to said first pulse rate divided by M; first counter means responsive to said pulses at said second pulse rate and also responsive to said means defining a time period to be subdivided, said first counter means being operative to count the number of pulses at said second pulse rate occurring during said time period to be subdivided; latch means to store the count stored in said first counter means at the conclusion of a time period; a second counter means, responsive to said latch and to said pulses at said first pulse rate during the next time period to produce a pulse at its output for every N pulses input thereto at said first rate where N is the number stored in said latch means, said second counter producing M pulses at its output during the period to be subdivided.

Claim 10

The circuit of claim 7 additionally including first scaling means to adjust the rate of said first pulse rate.

Claim 11

The circuit of claim 7 or 8 additionally including second scaling means to adjust the rate of said pulses applied to said second counter means independently of said first pulse rate.

Claim 12

The circuit of claim 7 wherein M is a power of 10.

Claim 13

The circuit of claim 8 wherein M is 1000.

Claim 14

The circuit of claim 1 wherein said means defining said time period to be subdivided includes a second latch which is set at the beginning of said period to be subdivided and reset at the end of said period to be subdivided.

Claim 15

A circuit for dividing each of a plurality of repeating time periods into a plurality of subintervals, each such time period being a length which may be different from either the preceding or succeding time period, comprising, in combination: means producing a start indication and a stop indication at the beginning and the end of each said repeating time period; an oscillator producing pulses at a frequency f 0 ; at least one scaling circuit responsive to said oscillator to procduce pulses at a rate of Nf 0 where N is a number between 0 and 1; ; means responsive to said scaling circuit to produce pulses at a frequency of Nf 0 /M; first counter means for counting said pulses at a frequency of Nf 0 /M occurring between each said start indication and the follwoing stop indication, the count so derived being designated P; means to store the count P after each successive stop indication; second counter means responsive to said pulses at a frequency of Nf 0 and to the count P in said means to store the count P to produce a pulse at its output each time said second pulse counter has counted P pulses at frequency Nf 0 .

Claim 16

A circuit for dividing each of a plurality of repeating time periods into a plurality of subintervals, each such time period being a length which may be different from either the preceding or succeding time period, comprising, in combination: means producing a start indication and a stop indication at the beginning and the end of each said repeating time period; an oscillator producing pulses at a frequency f 0 ; at least one scaling circuit responsive to said oscillator to procduce pulses at a rate of Nf 0 where N is a number between 0 and 1; ; means responsive to said scaling circuit to produce pulses at a frequency of Nf 0 /M; first counter means for counting said pulses at a frequency of Nf 0 /M occurring between each said start indication and the follwoing stop indication, the count so derived being designated P; means to store the count P after each successive stop indication; second counter means responsive to said pulses at a frequency of Nf 0 and to the count P in said means to store the count P to produce a pulse at its output each time said second pulse counter has counted P pulses at frequency Nf 0 .

Claim 17

The circuit of claim 13 additionally including a further scaling circuit for scaling the frequency of pulses counted by said second counter.

Claim 18

The circuit of claim 13 where M is a power of 10.

Claim 19

The circuit of claim 13 where M is 1000.

Claim 20

A circuit for dividing a time period, which is gradually changeable in length from one period to the next, into a fixed number of subintervals comprising, in combination: a first source of pulses; a control signal which is active between the beginning and the end of a period to be divided into a plurality of parts, said control signal being characterized in that the active state between the beginning and the end of said period is variable in time from one period to the next; a first counter circuit responsive to said pulses and to said control signal to count said pulses while said control signal is active; a latch circuit to store the content of said first counter during the time between the end of one period and the beginning of the next period, the stored count being designated N; means to reset said first counter after said latch is filled and before the beginning of said next period; a second source of pulses; a second counter responsive to said count N in said latch and to said second source of pulses to produce an output pulse for every N pulses from said second source of pulses.

Claim 21

A circuit for dividing a time period, which is gradually changeable in length from one period to the next, into a fixed number of subintervals comprising, in combination: a first source of pulses; a control signal which is active between the beginning and the end of a period to be divided into a plurality of parts, said control signal being characterized in that the active state between the beginning and the end of said period is variable in time from one period to the next; a first counter circuit responsive to said pulses and to said control signal to count said pulses while said control signal is active; a latch circuit to store the content of said first counter during the time between the end of one period and the beginning of the next period, the stored count being designated N; means to reset said first counter after said latch is filled and before the beginning of said next period; a second source of pulses; a second counter responsive to said count N in said latch and to said second source of pulses to produce an output pulse for every N pulses from said second source of pulses.

Claim 22

The circuit of claim 17 wherein the frequency of said second source of pulses is substantially M times the frequency of said first source.

Claim 23

The circuit of claim 18 where M is a power of 10.

Claim 24

The circuit of claim 18 where M is 1000.

Claim 25

A circuit for producing a plurality of control signals for a selectable percentage of a time period during which a known number of clock pulses occur, the circuit comprising, in combination: n counters where n is an integer, each said counter being settable and, in response to clock pulses applied to its clock input, each said counter will count down; means coupled to each said counter to set each counter to a selectable value prior to the time period when said clock pulses occur; means to apply the clock pulses to only one said counter at a time until it counts to zero whereat the clock pulses are applied to another said n counter; means responsive to each said counter when it is being counted down to produce a unique control signal for controlling a device coupled thereto; and means to actuate a selected one of said control signals whenever all said counters are zero or when one selected counter is not zero.

Claim 26

A circuit for producing a plurality of control signals for a selectable percentage of a time period during which a known number of clock pulses occur, the circuit comprising, in combination: n counters where n is an integer, each said counter being settable and, in response to clock pulses applied to its clock input, each said counter will count down; means coupled to each said counter to set each counter to a selectable value prior to the time period when said clock pulses occur; means to apply the clock pulses to only one said counter at a time until it counts to zero whereat the clock pulses are applied to another said n counter; means responsive to each said counter when it is being counted down to produce a unique control signal for controlling a device coupled thereto; and means to actuate a selected one of said control signals whenever all said counters are zero or when one selected counter is not zero.

Claim 27

The circuit of claim 21 additionally including means to select which said unique control signal is actuated when a given counter is counted down.

Claim 28

The circuit of claim 21 or 22 wherein said selected counter is set to a value less than the number of pulse counts desired to occur while said selected control signal is actuated.

Claim 29

The circuit of claim 21 or 22 wherein said selected counter is set to a value of one half the number of pulse counts desired to occur while said selected control signal is actuated.