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US4450433A
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D/A Converting circuit having two D/A converters for decoding and converting a digital signal into an analog signal
Assignee: Victor Company of Japan Ltd
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Filing: 1982-01-27
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Granted: 1984-05-22
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Expires: 2002-01-27
Abstract
Abstract A D/A converting circuit comprises two data selectors and two D/A converters having an external reference input terminal. A decoder responsive to several bits including the MSB of the input digital signal to be converted into an analog signal is provided to detect whether the input digital signal represents an analog signal magnitude which is greater than the full-scale value of the analog signal or not, and thus expansion-nonexpansion operation of the D/A converting circuit is controlled so that an m-bit D/A converter can be used, as the first D/A converter, to handle an n-bit digital signal where n>m. The first D/A converter receives m-bit information including the MSB in expansion mode, and receives m-bit information including the LSB in nonexpansion mode. The second D/A converter receives K-bit information (K=n-m) including the LSB of the input digital signal in expansion mode, and receives a predetermined digital data from a fixed data circut in nonexpansion mode. The second D/A converter performs D/A conversion by using a fixed voltage, and the output analog voltage of the second D/A converter is added to the fixed voltage prior to being fed to the first D/A converter as its reference voltage when expansion is required.
Inventors
- 👤 Masaru Moriyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:41
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/74
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
390 words
A D/A converting circuit comprising: (a) a decoder responsive to at least two bits of an input digital signal to be converted into an analog signal, one of said two bits being an MSB of said input digital signal, said decoder producing an output signal indicating that the magnitude of an analog signal represented by the input digital signal is greater than a predetermined value or not; (b) a first data selector controlled by the output signal from said decoder for selecting, as its output data, one of two sets of consecutive bits of said input digital signal, one of said two sets including said MSB and the other including an LSB of said input digital signal; (c) a first D/A converter having an external reference voltage input terminal, and being responsive to the output data from said first data selector for producing an output analog signal by using a first reference voltage applied to said external reference voltage input terminal; (d) a digital data generator for producing a predetermined digital data; (e) a second data selector controlled by said output signal from said decoder for selecting, as its output data, one of a set of consecutive bits of said input digital signal including said LSB, and said predetermined digital data from said digital data generator; (f) a second D/A converter having an external reference voltage input terminal, and being responsive to the output data from said second data selector for producing an output analog signal by using a second reference voltage applied to said external reference voltage input terminal, said second D/A converter producing a voltage having a specific relationship with respect to said second reference voltage when said predetermined digital data is applied thereto via said second data selector; (g) a D.C. voltage source for producing a predetermined voltage which is fed to said external reference voltage input terminal of said second D/A converter as said second reference voltage; and (h) means for producing said first reference voltage fed to said external reference voltage input terminal of said first D/A converter, said means being controlled by said output signal from said decoder for supplying said external reference voltage input terminal of said first D/A converter with the sum of said second reference voltage and the output voltage of said second D/A converter, or only said second reference voltage.
Claim 2
Dependent Claim
390 words
A D/A converting circuit comprising: (a) a decoder responsive to at least two bits of an input digital signal to be converted into an analog signal, one of said two bits being an MSB of said input digital signal, said decoder producing an output signal indicating that the magnitude of an analog signal represented by the input digital signal is greater than a predetermined value or not; (b) a first data selector controlled by the output signal from said decoder for selecting, as its output data, one of two sets of consecutive bits of said input digital signal, one of said two sets including said MSB and the other including an LSB of said input digital signal; (c) a first D/A converter having an external reference voltage input terminal, and being responsive to the output data from said first data selector for producing an output analog signal by using a first reference voltage applied to said external reference voltage input terminal; (d) a digital data generator for producing a predetermined digital data; (e) a second data selector controlled by said output signal from said decoder for selecting, as its output data, one of a set of consecutive bits of said input digital signal including said LSB, and said predetermined digital data from said digital data generator; (f) a second D/A converter having an external reference voltage input terminal, and being responsive to the output data from said second data selector for producing an output analog signal by using a second reference voltage applied to said external reference voltage input terminal, said second D/A converter producing a voltage having a specific relationship with respect to said second reference voltage when said predetermined digital data is applied thereto via said second data selector; (g) a D.C. voltage source for producing a predetermined voltage which is fed to said external reference voltage input terminal of said second D/A converter as said second reference voltage; and (h) means for producing said first reference voltage fed to said external reference voltage input terminal of said first D/A converter, said means being controlled by said output signal from said decoder for supplying said external reference voltage input terminal of said first D/A converter with the sum of said second reference voltage and the output voltage of said second D/A converter, or only said second reference voltage.
Claim 3
Dependent Claim
57 words
A D/A converting circuit as claimed in claim 1, wherein the first reference voltage producing means comprises a switching circuit for switching the output voltage from said voltage source and the output voltage from said second D/A converter, and an adder arranged to add the output voltage from said second D/A converter to said second reference voltage.
Claim 4
Dependent Claim
18 words
A D/A converting circuit as claimed in claim 1, wherein said decoder comprises at least one EX-OR gate.
Claim 5
Dependent Claim
39 words
A D/A converting circuit as claimed in claim 1, further comprising first and second latch circuits respectively interposed between said first data selector and said first D/A converter, and between said second data selector and said second D/A converter.
Claim 6
Dependent Claim
79 words
A D/A converting circuit as claimed in claim 1, wherein said digital data generator is arranged to produce said predetermined data so that said second D/A converter produces, when said predetermined data is fed to said second D/A converter, a voltage expressed by V/2K wherein V is said second reference voltage, and K is the difference between the number of entire bits of said input digital signal and the number of entire bits applied to said first D/A converter.
Claim 7
Dependent Claim
51 words
A D/A converting circuit as claimed in claim 1, wherein the number of bits of said input digital signal applied to said second D/A converter equals the difference between the number of entire bits of said input digital signal and the number of entire bits applied to said first D/A converter.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-22 | 1987-11-21 | 1988-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-22 | 1991-11-21 | 1992-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-22 | 1995-11-21 | 1996-05-22 | $7700.00 | Window Closed / Lapsed |