US4450365A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital logic buffer for converting single polarity analog signals to dual polarity analog signals
Assignee: Intel Corp
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Filing: 1981-09-14
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Granted: 1984-05-22
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Expires: 2001-09-14
Abstract
Abstract A digital logic buffer device for generating dual polarity analog signals is described. In the presently preferred embodiment, buffer receives the positive polarity analog output of a digital-to-analog converter (V DAC ), and a sign bit. If the sign bit indicates that a positive polarity is required, the buffer will output approximately V DAC . If a negative polarity is required, aproximately -V DAC will be generated.
Inventors
- 👤 Marcian E. Hoff, Jr.
- 👤 Marshall A. Townsend
- 👤 Stephen F. Dreyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:43
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
374 words
A buffer for converting a first signal having a single polarity to a second signal having a dual polarity, comprising: a capacitor having a first and second terminal; a first switching means, coupled to a first control line for controlling switching, for selectively coupling said first terminal of said capacitor to a source of said first signal and charging said capacitor; a second switching means, coupled to a second control line for controlling switching, for selectively coupling said first terminal of said capacitor to a first potential, and for discharging the charge on said capacitor; a third switching means, coupled to a third control line for controlling switching, for coupling said second terminal of said capacitor to said first potential and discharging said capacitor; a computer means for selecting which polarity of said dual polarities is required; a waveform generation means, coupled through said first, second and third control lines to said first, second and third switching means, and coupled to said selecting means, for generating a first set of waveforms to control said first, second and third switching means when one polarity of said dual polarities is selected, and a second set of waveforms to control said first, second and third switching means when the other polarity of said dual polarities is selected; said first set of waveforms for first causing said second and third switching means to couple said first and second terminal of said capacitor to said first potential, next causing said third switching means to decouple said second terminal from said first potential, and then causing said first switching means to couple said first terminal to said first signal having a single polarity, and said second set of waveforms for first causing said first switching means to couple said first terminal of said capacitor to said first signal having a single polarity and said third switching means to couple said second terminal of said capacitor to said first potential; and then causing said third switching means to decouple said second terminal from said first potential and said second switching means to couple said first terminal to said first potential; whereby said second signal having said dual polarity is generated from said first signal at said second terminal of said capacitor.
Claim 2
Dependent Claim
374 words
A buffer for converting a first signal having a single polarity to a second signal having a dual polarity, comprising: a capacitor having a first and second terminal; a first switching means, coupled to a first control line for controlling switching, for selectively coupling said first terminal of said capacitor to a source of said first signal and charging said capacitor; a second switching means, coupled to a second control line for controlling switching, for selectively coupling said first terminal of said capacitor to a first potential, and for discharging the charge on said capacitor; a third switching means, coupled to a third control line for controlling switching, for coupling said second terminal of said capacitor to said first potential and discharging said capacitor; a computer means for selecting which polarity of said dual polarities is required; a waveform generation means, coupled through said first, second and third control lines to said first, second and third switching means, and coupled to said selecting means, for generating a first set of waveforms to control said first, second and third switching means when one polarity of said dual polarities is selected, and a second set of waveforms to control said first, second and third switching means when the other polarity of said dual polarities is selected; said first set of waveforms for first causing said second and third switching means to couple said first and second terminal of said capacitor to said first potential, next causing said third switching means to decouple said second terminal from said first potential, and then causing said first switching means to couple said first terminal to said first signal having a single polarity, and said second set of waveforms for first causing said first switching means to couple said first terminal of said capacitor to said first signal having a single polarity and said third switching means to couple said second terminal of said capacitor to said first potential; and then causing said third switching means to decouple said second terminal from said first potential and said second switching means to couple said first terminal to said first potential; whereby said second signal having said dual polarity is generated from said first signal at said second terminal of said capacitor.
Claim 3
Dependent Claim
17 words
The buffer defined by claim 1 wherein the source of said first signal is a digital-to-analog converter.
References Cited (Backward Citations)
US3471714A
Cited
US4282447A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-22 | 1987-11-21 | 1988-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-22 | 1991-11-21 | 1992-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-22 | 1995-11-21 | 1996-05-22 | $7700.00 | Window Closed / Lapsed |