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US4450321A
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Circuit for producing noise generation for sound masking
Assignee: Individual
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Filing: 1981-12-08
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Granted: 1984-05-22
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Expires: 2001-12-08
Abstract
Abstract An apparatus and circuit is disclosed for the generation of a masking sound noise by which unwanted noise may be overcome without undue and unwanted sound levels. The apparatus and circuits have at least two multi-stage shift registers in which the last register sends an input signal to a first exclusive OR gate and to this same OR gate an intermediate connection to the shift register is made. The output from this first OR gate is sent to the first stage of the register and this same signal is sent as an output to a second exclusive OR gate. Each shift of each register is pulsed by an asynchronous clock. A second exclusive OR gate receives the output signals from each of the first OR gates and sends the output signal to a divide-by-counter and the output therefrom is sent to amplifying means and one or more speakers.
Inventors
- 👤 William D. Quigley
- 👤 Philip H. Nelson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:14
CPC Classifications
H; H04; H04K; H04K3/00; H04K3/80; H04K3/82; H04K3/825; G; G10; G10K; G10K11/00; G10K11/16; G10K11/175; G10K11/1752; G10K11/1754; H04K2203/00; H04K2203/10; H04K2203/12; H04K3/40; H04K3/42; H04K3/43
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
197 words
Apparatus and circuit for generating audible masking noise which is a yield of a random bit stream with an indeterminate period to repeat its pattern, said noise producing apparatus including: (a) at least two multi-stage shift registers, each with a first conducting means as an input to a first exclusive OR gate; (b) an input signal carried from an intermediate shift from said multi-stage shift register and providing another input to said first exclusive OR gate; (c) an asynchronous clock connected to each stage of said multi-stage register, said clock associated with each and only one multi-stage register and to feed pulse signals to each shift used in said register; (d) output conducting means from said first exclusive OR gate with said output leading from said first exclusive OR gate to and as an input to the multi-stage shift register and from this same output feeding to a conducting means an output signal; (e) a second exclusive OR gate which receives as inputs the output signals from the two first exclusive OR gates, and (f) an output signal from this second exclusive OR gate as a random bit stream with an indeterminate period to repeat its pattern.
Claim 2
Dependent Claim
197 words
Apparatus and circuit for generating audible masking noise which is a yield of a random bit stream with an indeterminate period to repeat its pattern, said noise producing apparatus including: (a) at least two multi-stage shift registers, each with a first conducting means as an input to a first exclusive OR gate; (b) an input signal carried from an intermediate shift from said multi-stage shift register and providing another input to said first exclusive OR gate; (c) an asynchronous clock connected to each stage of said multi-stage register, said clock associated with each and only one multi-stage register and to feed pulse signals to each shift used in said register; (d) output conducting means from said first exclusive OR gate with said output leading from said first exclusive OR gate to and as an input to the multi-stage shift register and from this same output feeding to a conducting means an output signal; (e) a second exclusive OR gate which receives as inputs the output signals from the two first exclusive OR gates, and (f) an output signal from this second exclusive OR gate as a random bit stream with an indeterminate period to repeat its pattern.
Claim 3
Dependent Claim
33 words
Apparatus and circuit as in claim 1 which further includes a divide-by-counter added to receive the output signal from said second exclusive OR gate and from said counter to generate an output signal.
Claim 4
Dependent Claim
49 words
Apparatus and circuit as in claim 1 in which the shift register is odd in the number of shifts and the output signal sent to the first exclusive OR gate is from the last shift and from a shift intermediate that shift which is after an even number shift.
Claim 5
Dependent Claim
15 words
Apparatus and circuit as in claim 3 in which the multi-shift register has seventeen stages.
Claim 6
Dependent Claim
64 words
Apparatus and circuit as in claim 2 in which there is provided more than two multi-shift registers and with each added shift register there is an added exclusive OR gate which receives as inputs the output of the second exclusive OR gate and the output signal from the added shift register, the output of this added exclusive OR gate being sent to the divide-by-counter.
Claim 7
Dependent Claim
20 words
Apparatus and circuit as in claim 4 in which there is provided a further output signal sent before the divide-by-counter.
Claim 8
Dependent Claim
31 words
Apparatus and circuits as in claim 1 which subsequent to the divide-by-counter includes a spectrum shaping filter, an amplitude control, an amplifier and one or more speakers and a power source.
Claim 9
Dependent Claim
24 words
Apparatus and circuits as in claim 6 in which there is provided a variable resistor to adjust the capacity of the spectrum shaping filter.
Claim 10
Dependent Claim
32 words
Apparatus and circuits as in claim 1 in which the small electronic components are mounted on and attached to printed circuit boards removably mountable in the apparatus for eacy replacement and repair.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-22 | 1987-11-21 | 1988-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-22 | 1991-11-21 | 1992-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-22 | 1995-11-21 | 1996-05-22 | $7700.00 | Window Closed / Lapsed |