Variable capacitor

Claim 2

A variable capacitor, comprising a semiconductor substrate; a plurality of variable capacitor arrangements which are provided at spaced locations on said substrate, which each include depletion layer control means for controlling a depletion layer in an adjacent region of said substrate, and which each include capacity reading means for providing at a capacity reading terminal a capacitance which is dependent on the size of said depletion layer and the carrier concentration of said substrate in the region of said depletion layer; and bias voltage applying means for applying a bias voltage from a variable voltage source to said depletion layer control means; said semiconductor substrate having a different carrier concentration in the region of each of said capacity reading means.

Claim 3

A variable capacitor as claimed in claim 1, wherein the carrier concentration of said semiconductor substrate gradually increases in a direction therealong.

Claim 4

A variable capacitor as claimed in claim 10, including means defining insulated regions between respective said variable capacitor arrangements.

Claim 5

A variable capacitor as claimed in claim 1, wherein each said depletion layer control means includes means defining a PN junction.

Claim 6

A variable capacitor as claimed in claim 1, wherein each said depletion layer control means includes an insulator layer provided on said semiconductor substrate and an electrode provided on said insulator layer.

Claim 7

A variable capacitor as claimed in claim 1, wherein each said depletion layer control means includes means defining a Shottky-barrier structure.

Claim 8

A variable capacitor as claimed in claim 1, wherein each said capacity reading means includes means defining a PN junction.

Claim 9

A variable capacitor as claimed in claim 1, wherein each said capacity reading means includes an insulator layer provided on said semiconductor substrate and an electrode provided on said insulator layer.

Claim 10

A variable capacitor as claimed in claim 1, wherein each said capacity reading means includes means defining a Schottky-barrier structure.

Claim 11

A variable capacitor, comprising: a semiconductor substrate, said substrate having a different carrier concentration in the region of each of a plurality of spaced first locations thereon; plural depletion layer control electrode means, each said depletion layer control electrode means being provided on said substrate at a respective one of said first locations; plural capacitance electrode means, each said capacitance electrode means being provided on said substrate in the region of a respective one of said first locations and being connected to a common first terminal; a second terminal and means connecting said second terminal to a second location on said substrate which is spaced from each of said first locations; and means for applying a common variable bias voltage between said second terminal and each of said depletion layer control electrode means, said bias voltage producing a depletion layer in said substrate in the region of each said depletion layer control electrode means, each said depletion layer having a thickness which is dependent on the magnitude of said bias voltage and each said depletion layer inducing a capacitance between the associated capacitance electrode means and said second location, the magnitude of such capacitance being dependent on the magnitude of said bias voltage and on the carrier concentration of said substrate in the region of the associated capacitance electrode means, the total capacitance provided between said first and second terminals being the sum of the capacitances between said second terminal and each of said capacitance electrode means and decreasing progressively as said bias voltage is increased.

Claim 12

A variable capacitor, comprising: a semiconductor substrate, said substrate having a different carrier concentration in the region of each of a plurality of spaced first locations thereon; plural depletion layer control electrode means, each said depletion layer control electrode means being provided on said substrate at a respective one of said first locations; plural capacitance electrode means, each said capacitance electrode means being provided on said substrate in the region of a respective one of said first locations and being connected to a common first terminal; a second terminal and means connecting said second terminal to a second location on said substrate which is spaced from each of said first locations; and means for applying a common variable bias voltage between said second terminal and each of said depletion layer control electrode means, said bias voltage producing a depletion layer in said substrate in the region of each said depletion layer control electrode means, each said depletion layer having a thickness which is dependent on the magnitude of said bias voltage and each said depletion layer inducing a capacitance between the associated capacitance electrode means and said second location, the magnitude of such capacitance being dependent on the magnitude of said bias voltage and on the carrier concentration of said substrate in the region of the associated capacitance electrode means, the total capacitance provided between said first and second terminals being the sum of the capacitances between said second terminal and each of said capacitance electrode means and decreasing progressively as said bias voltage is increased.

Claim 13

The variable capacitor according to claim 10, including two said depletion layer control electrode means in the region of each of said first locations on said semiconductor substrate.

Claim 14

The variable capacitor according to claim 10, including means defining an insulating region between adjacent said first locations on said semiconductor substrate.

Claim 15

The variable capacitor according to claim 10, wherein the carrier concentration in said semiconductor substrate increases progressively in a direction, and wherein said first locations are provided at spaced intervals along said substrate in said direction.

Claim 16

The variable capacitor according to claim 10, wherein one of said depletion layer control electrode means and said capacitance electrode means includes a layer of semiconductor material provided on said substrate and an electrode provided on said semiconductor layer, one of said substrate and said semiconductor layer being a P-type semiconductor and the other of said substrate and said semiconductor layer being an N-type semiconductor.

Claim 17

The variable capacitor according to claim 10, wherein one of said depletion layer control electrode means and said capacitance electrode means includes an insulator layer provided on said substrate and an electrode provided on said insulator layer.

Claim 18

The variable capacitor according to claim 10, where one of said depletion layer control electrode means and said capacitance electrode means includes a metallic-semiconductive barrier provided on said semiconductor substrate and a metallic electrode provided on said metallic-semiconductor barrier.

Claim 19

The variable capacitor according to claim 10, wherein said means connecting said second terminal to said second location on said substrate includes an electrode provided on said substrate at said second location and connected to said second terminal.

Claim 20

The variable capacitor according to claim 17, wherein said substrate has first and second surfaces on opposite sides thereof, wherein said depletion layer control electrode means and said capacitance electrode means are provided on said first surface of said substrate, and wherein said electrode is provided on said second surface of said substrate.

Claim 21

The variable capacitor according to claim 10, wherein the capacitance between each said capacitance electrode means and said second location changes rapidly from a maximum value to a minimum value when said bias voltage is increased above a threshold voltage, and wherein said threshold voltage is dependent on the carrier concentration in said substrate in the region of such capacitance electrode means, each said capacitance electrode means thereby having a unique threshold voltage associated therewith, and wherein said progressive decrease of said total capacitance between said first and second terminals occurs in a steplike manner as said bias voltage is increased.