Patent US4447893A successfully refreshed from Google Patents.
US4447893A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor read only memory device
Assignee: Fujitsu Ltd
•
Filing: 1981-07-27
•
Granted: 1984-05-08
•
Expires: 2001-07-27
Abstract
Abstract A semiconductor read only memory device comprises bit lines, word lines, a load transistor, a multiplexer including a plurality of transistors, and a memory cell array in which each memory cell has one transistor having a gate connected to one of the word lines and corresponding to one of the bit lines connected to the transistors of the multiplexer. A gate transistor is inserted between the load transistor and the multiplexer, and a gate voltage control circuit, for selectively providing a higher level signal and a lower level signal, is connected to the gate transistor.
Inventors
- 👤 Jyoji Murakami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:38
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
180 words
A semiconductor read only memory device operatively connectable to receive a clock signal, connected to a voltage source and having a preparation period and a reading period, comprising: a plurality of bit lines; a plurality of word lines; a load transistor electrically connected to the voltage source; a multiplexer including a plurality of transistors each of which is elelctrically connected to one of said plurality of bit lines; a memory cell array in which each memory cell has one transistor having a gate electrically connected to one of said plurality of word lines and a source or a drain electrically connected to one of said plurality of bit lines; a gate transistor connected between said load transistor and said multiplexer; and gate voltage control means, connected to said gate transistor and operatively connectable to receive the clock signal which indicates whether the memory device is in the preparation period or the reading period, for selectively providing, to the gate of said gate transistor, a first level signal during the preparation period and a second level signal during the reading period.
Claim 2
Dependent Claim
180 words
A semiconductor read only memory device operatively connectable to receive a clock signal, connected to a voltage source and having a preparation period and a reading period, comprising: a plurality of bit lines; a plurality of word lines; a load transistor electrically connected to the voltage source; a multiplexer including a plurality of transistors each of which is elelctrically connected to one of said plurality of bit lines; a memory cell array in which each memory cell has one transistor having a gate electrically connected to one of said plurality of word lines and a source or a drain electrically connected to one of said plurality of bit lines; a gate transistor connected between said load transistor and said multiplexer; and gate voltage control means, connected to said gate transistor and operatively connectable to receive the clock signal which indicates whether the memory device is in the preparation period or the reading period, for selectively providing, to the gate of said gate transistor, a first level signal during the preparation period and a second level signal during the reading period.
Claim 3
Dependent Claim
242 words
A semiconductor read only memory device operatively connectable to receive a clock signal and an inverted clock signal, connected to a voltage source, and having a reading preparation mode and a reading mode, comprising: a memory cell array; a multiplexer operatively connected to said memory cell array; a load transistor operatively connected to the voltage source; a gate transistor operatively connected to said load transistor and said multiplexer; and a gate voltage control circuit, operatively connectable to receive the clock signal and the inverted clock signal and operatively connected to said gate transistor, for providing a first level signal to said gate transistor during the reading preparation mode of said semiconductor read only memory device and for providing a second level signal to said gate transistor during the reading mode of said semiconductor read only memory device, said gate voltage control circuit comprising: a first transistor operatively connected to the voltage source and operatively connected to said gate transistor at a first node; a second transistor operatively connected at said first node; a third transistor operatively connectable to receive the clock signal and operatively connected to said second transistor; a fourth transistor operatively connectable to receive the inverted clock signal, operatively connected to said third transistor at a second node and operatively connected to a reference potential; and a fifth transistor operatively connected to said second and third transistors, operatively connected at said second node and operatively connected to the reference potential.
Claim 4
Dependent Claim
242 words
A semiconductor read only memory device operatively connectable to receive a clock signal and an inverted clock signal, connected to a voltage source, and having a reading preparation mode and a reading mode, comprising: a memory cell array; a multiplexer operatively connected to said memory cell array; a load transistor operatively connected to the voltage source; a gate transistor operatively connected to said load transistor and said multiplexer; and a gate voltage control circuit, operatively connectable to receive the clock signal and the inverted clock signal and operatively connected to said gate transistor, for providing a first level signal to said gate transistor during the reading preparation mode of said semiconductor read only memory device and for providing a second level signal to said gate transistor during the reading mode of said semiconductor read only memory device, said gate voltage control circuit comprising: a first transistor operatively connected to the voltage source and operatively connected to said gate transistor at a first node; a second transistor operatively connected at said first node; a third transistor operatively connectable to receive the clock signal and operatively connected to said second transistor; a fourth transistor operatively connectable to receive the inverted clock signal, operatively connected to said third transistor at a second node and operatively connected to a reference potential; and a fifth transistor operatively connected to said second and third transistors, operatively connected at said second node and operatively connected to the reference potential.
Claim 5
Dependent Claim
29 words
A semiconductor read only memory device as set forth in claim 2, wherein said gate transistor is a field effect transistor having a gate connected at said first node.
Claim 6
Dependent Claim
25 words
A semiconductor read only memory device as set forth in claim 3, wherein said first, second, third, fourth and fifth transistors are field effect transistors.
References Cited (Backward Citations)
US3942162A
Cited
US4110840A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-08 | 1987-11-07 | 1988-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-08 | 1991-11-07 | 1992-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-08 | 1995-11-07 | 1996-05-08 | $7700.00 | Window Closed / Lapsed |