Multiphase inverter drive circuit with synchronized switching delay feature

Claim 2

A circuit for leading edge delay in synchronized switching waveforms, comprising: a first power terminal; a second power terminal a plurality of output terminals; a plurality of complementary paired switches, each of said pairs associated with one of said output terminals and having a first and second switch, the first and second switch of each of said paired switches alternately connecting said first and second power terminals to the associated one of said output terminals; means for generating a plurality of synchronized reference pulse waveforms and the complements thereof, each of said reference waveforms and the complements thereof associated with each of said paired switches for switching thereof; means for generating a delay pulse having a variable width; steering means for receiving said reference waveforms and said delay pulse and generating a blanking pulse waveform for each of said reference waveforms and the complement waveforms thereof, each pulse therein having a width equal to the width of said delay pulse, the leading edge of each of the pulses in each of said blanking waveforms directly corresponding to the leading edge in the corresponding pulse of said reference waveforms and said complement waveforms; blanking means for receiving said reference waveforms, said complement waveforms and said blanking waveforms, said blanking means outputting a plurality of corresponding delayed pulse waveforms, each pulse therein having the trailing edge thereof directly corresponding to the trailing edge of each of the pulses in each of the corresponding one of said reference waveforms and said complements thereof and the leading edges thereof delayed by the width of said delay pulse, each of said delayed waveforms for driving each of the first and second switches of each of said paired switches wherein closing of the first or second switch in each of said paired switches is delayed to allow the complementary switch thereof sufficient time to open; and an inhibit circuit for generating an inhibit signal to inhibit said blanking means from generating said delayed waveforms corresponding to said complementary waveforms.

Claim 3

The circuit of claim 1 wherein both the first and second switch of each of said paired switches comprise a pair of NPN transistors connecting in a Darlington configuration.

Claim 4

The circuit of claim 1 wherein said means for generating said reference waveforms and the complement thereof comprises: an oscillator having a constant frequency; a frequency divider for dividing the frequency of said oscillator, said frequency divider outputting the plurality of said reference waveforms; and a plurality of inverters, the input of each of the inverters for receiving one of said reference waveforms and each of the outputs thereof for outputting said complement waveforms.

Claim 5

The circuit of claim 1 wherein said means for generating a delay pulse comprises a monostable multivibrator having a variable pulse width.

Claim 6

The circuit of claim 1 wherein said blanking means comprises a plurality of AND gate logic circuits each having at least two inputs, one of said inputs for receiving one of said reference waveforms and the complements thereof and the other of said inputs for receiving one of said blanking waveforms such that each of the pulses in each of said blanking waveforms inhibits the output of the respective one of said AND gates at the leading edge of each of the pulses of the respective one of said first waveforms and the complements thereof and for a duration equal to the width of said delay pulse.

Claim 7

A circuit for delaying the leading edge of synchronized switching waveforms for a three-phase DC to AC converter, comprising: a first power terminal; a second power terminal; a first switching circuit having complementary first and second switches for alternately connecting said first and second power terminals to a first output terminal; a second switching circuit having complementary first and second switches for alternately connecting said first and second power terminals to a second output terminal; a third switching circuit having complementary first and second switches for alternately connecting said first and second power terminals to a third output terminal; means for synchronously generating a first reference pulse waveform having a 0° phase shift, a second reference pulse waveform having a 120°phase shift and a third reference pulse waveform having a 240° phase shift; means for receiving said first, second and third reference waveforms and generating corresponding first, second and third complementary waveforms respectively; means for generating a delay pulse that is synchronized with said first, second and third reference waveforms and having a variable width; steering means for receiving said first, second and third reference waveforms and said delay pulse and generating a separate blanking pulse for each pulse in said first, second and third reference waveforms and said first, second and third complementary waveforms, each of said blanking pulses having the leading edge thereof corresponding to the leading edge of the respective pulse of both said first, second and third reference waveforms and said first, second and third complementary waveforms and a pulse width equal to the pulse width of said delay pulse; blanking means fo receiving said first, second and third reference waveforms, said first, second and third complementary waveforms and said blanking pulses, said blanking means outputting delayed first, second and third reference waveforms and delayed first, second and third complementary waveforms to drive said first, second and third switching circuits, respectively, wherein said blanking pulse delays the leanding edge of each of the pulses in said first, second and third reference waveforms and said first, second and third complementary waveforms such that the opening of the first and second switch of each of said switching circuits is delayed to allow the complementary switch thereof sufficient time to close; and an inhibit circuit that generates an inhibit signal to inhibit said complementary delayed waveforms..

Claim 8

A circuit for delaying the leading edge of synchronized switching waveforms for a three-phase DC to AC converter, comprising: a first power terminal; a second power terminal; a first switching circuit having complementary first and second switches for alternately connecting said first and second power terminals to a first output terminal; a second switching circuit having complementary first and second switches for alternately connecting said first and second power terminals to a second output terminal; a third switching circuit having complementary first and second switches for alternately connecting said first and second power terminals to a third output terminal; means for synchronously generating a first reference pulse waveform having a 0° phase shift, a second reference pulse waveform having a 120°phase shift and a third reference pulse waveform having a 240° phase shift; means for receiving said first, second and third reference waveforms and generating corresponding first, second and third complementary waveforms respectively; means for generating a delay pulse that is synchronized with said first, second and third reference waveforms and having a variable width; steering means for receiving said first, second and third reference waveforms and said delay pulse and generating a separate blanking pulse for each pulse in said first, second and third reference waveforms and said first, second and third complementary waveforms, each of said blanking pulses having the leading edge thereof corresponding to the leading edge of the respective pulse of both said first, second and third reference waveforms and said first, second and third complementary waveforms and a pulse width equal to the pulse width of said delay pulse; blanking means fo receiving said first, second and third reference waveforms, said first, second and third complementary waveforms and said blanking pulses, said blanking means outputting delayed first, second and third reference waveforms and delayed first, second and third complementary waveforms to drive said first, second and third switching circuits, respectively, wherein said blanking pulse delays the leanding edge of each of the pulses in said first, second and third reference waveforms and said first, second and third complementary waveforms such that the opening of the first and second switch of each of said switching circuits is delayed to allow the complementary switch thereof sufficient time to close; and an inhibit circuit that generates an inhibit signal to inhibit said complementary delayed waveforms..

Claim 9

The circuit of claim 6 wherein the first and second complementary switches of said first, second and third switching circuits each comprise a pair of NPN transistors connected in a Darlington configuration.

Claim 10

The circuit of claim 6 wherein said means for synchronously generating comprises: an oscillator having a constant frequency; and a divide-by-six frequency divider for dividing the frequency of said oscillator, said frequency divider outputting said first, second and third reference waveforms.

Claim 11

The circuit of claim 6 wherein said means for generating said first, second and third complementary waveforms comprises an inverting logic circuit.

Claim 12

The circuit of claim 7 wherein said means for generating said delay pulse comprises a monstable multivibrator having a trigger input connected to the output of said oscillator, the pulse width thereof variable.

Claim 13

The circuit of claim 6 wherein said means for generating said delay pulse comprises a monostable multivibrator having a trigger input for receiving a trigger signal from said means for synchronously generating, the pulse width thereof variable.

Claim 14

The circuit of claim 6 wherein said steering means comprises a four to sixteen decoder having an A, B and C input for receiving said first, second and third reference waveforms and a D input thereof for receiving said delay pulse, said four to sixteen decoder outputting a pulse for both the leading edge and the trailing edge of each pulse in each of said reference waveforms to produce said blanking pulses.

Claim 15

The circuit of claim 6 wherein said blanking means comprises a plurality of AND logic circuits each having at least two inputs for receiving each of said reference waveforms and the complements thereof and each of the pulses in each of said blanking waveforms.