US4446384A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MIS Device including a substrate bias generating circuit
Assignee: Fujitsu Ltd
•
Filing: 1983-01-10
•
Granted: 1984-05-01
•
Expires: 2003-01-10
Abstract
Abstract A MIS device including a substrate bias generating circuit comprising: an oscillating circuit for generating clock signals; a pumping circuit comprised of a charging and discharging circuit and a bias circuit, for absorbing charges in a semiconductor substrate, and; a clamp circuit for clamping the potential of the substrate at a desired level.
Inventors
- 👤 Shigenobu Taira
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:22
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211; H10D89/213; H10D89/215; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
100 words
A MIS device including a substrate bias generating circuit for absorbing charges in a semiconductor substrate thereof, comprising: a bias circuit, connected to said semiconductor substrate, which performs charging and discharging operations upon said semiconductor substrate in accordance with clock signals so as to absorb said charges in said semiconductor substrate, and a clamp circuit connected between said semiconductor substrate and a predetermined reference power supply, the conductance of said clamp circuit being determined so as to satisfy I SS >>I BB where I BB is a substrate current and I SS is a current flowing through said clamp circuit.
Claim 2
Dependent Claim
100 words
A MIS device including a substrate bias generating circuit for absorbing charges in a semiconductor substrate thereof, comprising: a bias circuit, connected to said semiconductor substrate, which performs charging and discharging operations upon said semiconductor substrate in accordance with clock signals so as to absorb said charges in said semiconductor substrate, and a clamp circuit connected between said semiconductor substrate and a predetermined reference power supply, the conductance of said clamp circuit being determined so as to satisfy I SS >>I BB where I BB is a substrate current and I SS is a current flowing through said clamp circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-01 | 1987-10-31 | 1988-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-01 | 1991-10-31 | 1992-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-01 | 1995-10-31 | 1996-05-01 | $7700.00 | Window Closed / Lapsed |