Pull-in circuit for a digital phase locked loop

Claim 2

A fast pull-in digital phase locked loop circuit which obtains a phase difference between a single frequency signal and an output signal of said digital phase locked loop which is obtained by dividing a specified frequency with a dividing counter, comprising: a sample circuit which obtains two sample values of said single frequency signal at two points based on said output signal of said digital phase locked loop corresponding to a phase difference of π/2 radians of said single frequency signal, said two sample values each having a sign; a comparator circuit, operatively connected to said sample circuit, which determines a relationship of the absolute values of said two sample values; an amplitude ratio circuit, operatively connected to said sample circuit, which obtains an amplitude ratio of said two sample values; conversion means, operatively connected to said sample circuit, said comparator circuit, said amplitude ratio circuit and said dividing counter, for obtaining an initial value corresponding to said phase difference from the sign of said two sample values, the relationship determined by said comparator circuit and the amplitude ratio produced by said amplitude ratio circuit, and the initial value being set into said dividing counter; and pulse means, operatively connected to said dividing counter, for producing pulses in dependence upon a phase difference between said output signal and said single frequency signal.

Claim 3

A fast pull-in digital phase locked loop circuit as set forth in claim 1, wherein said comparator circuit comprises: an absolute value network, operatively connected to said sample circuit, which obtains the respective absolute values of said two sample values; and a subtractor, operatively connected to said absolute value network, which obtains a difference between the two absolute values produced by said absolute value network.

Claim 4

A fast pull-in digital phase locked loop circuit as set forth in claim 2, wherein said amplitude ratio circuit comprises: a selector, operatively connected to said absolute value network and said subtractor, and having first and second paths, which selectively connects the two outputs of said absolute value network to the first or second path in dependence upon the difference produced by said subtractor; a reciprocate network, operatively connected to said second path, which obtains a reciprocal of the absolute value received by the second path; and a multiplier, operatively connected to the first path and said reciprocate network, to which the signals sent from said first and second paths are input.

Claim 5

A fast pull-in digital phase locked loop circuit as set forth in claim 1, wherein said pulse means comprises: an oscillator outputting pulses at the specified frequency; a phase detector, operatively connected to said dividing counter, which inputs said output signal from said digital phase locked loop and said single frequency signal and detects a phase difference between these signals; and a remove tooth network, operatively connected to said oscillator, said dividing counter and said phase detector, which thins the output pulses of the oscillator outputting said specified frequency signal in accordance with the phase difference produced by said phase detector.

Claim 6

A fast pull-in digital phase locked loop circuit which obtains a phase difference between a single frequency signal and an output signal of said digital phase locked loop which is obtained by dividing the specified frequency with a dividing counter and pulls in the phase synchronization, comprising: a sample circuit which obtains two sample values of said single frequency signal at two points based on said output signal of said digital phase locked loop corresponding to a phase difference of π/2 radians of said single frequency signal, said two sample values each having a sign; a comparator circuit, operatively connected to said sample circuit, which obtains the relationship between absolute values of said two sample values; an amplitude ratio circuit, operatively connected to said sample circuit, which obtains an amplitude ratio of said two sampled values; conversion means, operatively connected to said sample circuit, said comparator circuit, said amplitude ratio circuit and said dividing counter, for obtaining a value corresponding to a supplementary angle of said phase difference from the signs of said two sample values, the relationship produced by said comparator circuit and the amplitude ratio produced by said amplitude ratio circuit, and said dividing counter stops operation for a period corresponding to said supplementary angle in accordance with the supplementary angle produced by said conversion table; and pulse means, operatively connected to said dividing counter, for producing pulses in dependence upon a phase difference between said output signal and said single frequency signal.

Claim 7

A fast pull-in digital phase locked loop circuit which obtains a phase difference between a single frequency signal and an output signal of said digital phase locked loop which is obtained by dividing the specified frequency with a dividing counter and pulls in the phase synchronization, comprising: a sample circuit which obtains two sample values of said single frequency signal at two points based on said output signal of said digital phase locked loop corresponding to a phase difference of π/2 radians of said single frequency signal, said two sample values each having a sign; a comparator circuit, operatively connected to said sample circuit, which obtains the relationship between absolute values of said two sample values; an amplitude ratio circuit, operatively connected to said sample circuit, which obtains an amplitude ratio of said two sampled values; conversion means, operatively connected to said sample circuit, said comparator circuit, said amplitude ratio circuit and said dividing counter, for obtaining a value corresponding to a supplementary angle of said phase difference from the signs of said two sample values, the relationship produced by said comparator circuit and the amplitude ratio produced by said amplitude ratio circuit, and said dividing counter stops operation for a period corresponding to said supplementary angle in accordance with the supplementary angle produced by said conversion table; and pulse means, operatively connected to said dividing counter, for producing pulses in dependence upon a phase difference between said output signal and said single frequency signal.

Claim 8

A fast pull-in digital phase locked loop circuit as set forth in claim 5, wherein said comparator circuit comprises: an absolute value network, operatively connected to said sample circuit, which takes respective absolute values of said two sample values; and a subtractor, operatively connected to said absolute value network, which obtains a difference between the absolute values produced by said absolute value network.

Claim 9

A fast pull-in digital phase locked loop circuit as set forth in claim 6, wherein said amplitude ratio circuit comprises: a selector, operatively connected to said absolute value network and said subtractor and having first and second paths, which selectively passes the outputs of said absolute value network to the first or second path in dependence upon the difference produced by said subtractor; a reciprocate network, operatively connected to the second path, which obtains a reciprocal of the absolute value received by the second path; and a multiplier, operatively connected to the first path and said reciprocate network, which inputs the signals sent from said first and second paths.

Claim 10

A fast pull-in digital phase locked loop circuit as set forth in claim 5, wherein said pulse means comprises: an oscillator outputting pulses of a specified frequency; a phase detector, operatively connected to said dividing counter, which inputs both said output signal from said digital phase locked loop and said single frequency signal and detects a phase difference between these signals; and a remove tooth network, operatively connected to said oscillator, said dividing counter and said phase detector, which thins the output pulses from the oscillator which outputs said specified frequency signal, in accordance with the difference produced by said phase detector.

Claim 11

A fast pull-in digital phase locked loop circuit as set forth in claim 8, further comprising: a down counter, operatively connected to said conversion table and said oscillator, which initially receives a value corresponding to said supplementary angle and counts down; a first gate, operatively connected to said down counter, said oscillator and said remove tooth network, which opens when the count of said down counter becomes zero and a second gate, operatively connected to said dividing counter and said first gate, which opens when the count of said dividing counter becomes zero.

Claim 12

A digital phase locked loop circuit operatively connectable to receive a start signal and a single frequency signal which is a digital representation of an analog single frequency signal and for generating a reference timing signal, comprising: clock means for generating a reference clock signal; pulse means, operatively connected to said clock means, for generating clock pulses in dependance upon the reference clock signal; count means, operatively connectable to receive the start signal and operatively connected to said pulse means, for counting the clock pulses under the control of the start signal and for generating the reference timing signal and a control signal in dependence upon the count; storage means, operatively connected to receive the single frequency signal and operatively connected to said count means, for storing first and second values of the single frequency signal in dependence upon the reference timing signal and the control signal; phase detection means, operatively connected to said count means and operatively connectable to receive the single frequency signal, for detecting a phase difference between the reference timing signal and the single frequency signal and for generating an inhibit signal in dependence upon the phase difference, the inhibit signal controlling said pulse means to inhibit the generation of the clock pulses and calculation means, operatively connected to said storage means and said count means, for determining the sign of said first and second values, for dividing the smaller of the first and second values by the larger of the first and second values and for generating a count value from the determining, comparing and dividing, the count value being input into said count means in dependence upon said start signal.

Claim 13

A digital phase locked loop circuit operatively connectable to receive a start signal and a single frequency signal which is a digital representation of an analog single frequency signal and for generating a reference timing signal, comprising: clock means for generating a reference clock signal; pulse means, operatively connected to said clock means, for generating clock pulses in dependance upon the reference clock signal; count means, operatively connectable to receive the start signal and operatively connected to said pulse means, for counting the clock pulses under the control of the start signal and for generating the reference timing signal and a control signal in dependence upon the count; storage means, operatively connected to receive the single frequency signal and operatively connected to said count means, for storing first and second values of the single frequency signal in dependence upon the reference timing signal and the control signal; phase detection means, operatively connected to said count means and operatively connectable to receive the single frequency signal, for detecting a phase difference between the reference timing signal and the single frequency signal and for generating an inhibit signal in dependence upon the phase difference, the inhibit signal controlling said pulse means to inhibit the generation of the clock pulses and calculation means, operatively connected to said storage means and said count means, for determining the sign of said first and second values, for dividing the smaller of the first and second values by the larger of the first and second values and for generating a count value from the determining, comparing and dividing, the count value being input into said count means in dependence upon said start signal.

Claim 14

A digital phase locked loop circuit operatively connectable to receive a start signal and a single frequency signal which is a digital representation of an analog single frequency signal and for generating a reference timing signal, comprising: clock means for generating a reference clock signal; gate means, operatively connected to said clock means, for passing therethrough the reference clock signal; pulse means, operatively connected to said gate means, for generating clock pulses in dependance upon the reference clock signal; first count means, operatively connected to said pulse means, for counting the clock pulses and for generating the reference timing signal and a control signal in dependence upon the count; storage means, operatively connectable to receive the single frequency signal and operatively connected to said count means, for storing first and second values of the single frequency signal in dependence the reference timing signal and the control signal; phase detection means, operatively connected to said first count means and operatively connectable to receive the single frequency signal, for detecting a phase difference between the reference timing signal and the single frequency signal and for generating an inhibit signal in dependence upon the phase difference, the inhibit signal controlling said pulse means to inhibit the generation of the clock pulses; calculation means, operatively connected to said storage means, for comparing the absolute values of said first and second values, for dividing the smaller of the first and second values by the larger of the first and second values and for generating a count value from the determining, comparing and dividing; second count means, operatively connected to said calculation means and said clock means, for counting down from the count value in dependence upon the reference clock signal; second gate means, operatively connectable to receive the start signal and operatively connected to said first count means, for passing therethrough the reference timing signal in dependence upon the start signal; and gate control means, operatively connected to said second count means, said second gate means, and said first gate means, for controlling said first gate means in dependence upon the output of said second count means and said reference timing signal.

Claim 15

A digital phase locked loop circuit operatively connectable to receive a start signal and a single frequency signal which is a digital representation of an analog single frequency signal and for generating a reference timing signal, comprising: clock means for generating a reference clock signal; gate means, operatively connected to said clock means, for passing therethrough the reference clock signal; pulse means, operatively connected to said gate means, for generating clock pulses in dependance upon the reference clock signal; first count means, operatively connected to said pulse means, for counting the clock pulses and for generating the reference timing signal and a control signal in dependence upon the count; storage means, operatively connectable to receive the single frequency signal and operatively connected to said count means, for storing first and second values of the single frequency signal in dependence the reference timing signal and the control signal; phase detection means, operatively connected to said first count means and operatively connectable to receive the single frequency signal, for detecting a phase difference between the reference timing signal and the single frequency signal and for generating an inhibit signal in dependence upon the phase difference, the inhibit signal controlling said pulse means to inhibit the generation of the clock pulses; calculation means, operatively connected to said storage means, for comparing the absolute values of said first and second values, for dividing the smaller of the first and second values by the larger of the first and second values and for generating a count value from the determining, comparing and dividing; second count means, operatively connected to said calculation means and said clock means, for counting down from the count value in dependence upon the reference clock signal; second gate means, operatively connectable to receive the start signal and operatively connected to said first count means, for passing therethrough the reference timing signal in dependence upon the start signal; and gate control means, operatively connected to said second count means, said second gate means, and said first gate means, for controlling said first gate means in dependence upon the output of said second count means and said reference timing signal.

Claim 16

A digital phase locked loop as set forth in claim 10 or 11, wherein said first and second values have signs, and wherein said calculation means comprises: absolute value means, operatively connected to said storage means, for generating the absolute values of said first and second values; subtract means, operatively connected to said absolute value means, for generating a selection signal in dependence upon the absolute value; selector means, operatively connected to said absolute value means and said subtract means, for selectively outputting the absolute values in dependence upon the selection signal; inverse means, operatively connected to said selector means, for inverting one of the absolute values; multiplier means, operatively connected to said selector means and said inverse means, for multiplying the inverted absolute value by the non-inverted absolute value and producing a multiplied value; and memory means, operatively connected to said multiplier means, said subtractor means and said storage means, for outputting the count value in dependence upon the signs of the first and second values, the selection signal and the multiplied value.