US4338574A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Carrier recovering circuit for phase modulated signal
Assignee: NEC Corp
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Filing: 1980-03-26
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Granted: 1982-07-06
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Expires: 2000-03-26
Abstract
Abstract The voltage controlled oscillator (VCO) in a phase-locked loop carrier recovery circuit is provided with two control signals, one based upon a phase error between the phase modulated carrier and VCO output and the other based upon a frequency error between the phase modulated carrier and VCO output.
Inventors
- 👤 Toshio Fujita
- 👤 Youichi Matsumoto
- 👤 Yoshimi Tagashira
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 06:01
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/087; H03L7/10; H03L7/113; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2271; H04L27/2273; H04L27/0014; H04L2027/0024; H04L2027/0026; H04L2027/0028; H04L2027/0044; H04L2027/0063; H04L2027/0067
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
236 words
A phase locked loop circuit comprising: a voltage-controlled oscillator for generating a reference phase signal in response to a control signal; phase detecting means for receiving an N-phase (N=2 n , n is a positive integer) phase-modulated carrier wave and said reference phase signal and for detecting said carrier wave on the basis of said reference phase signal, said phase detecting means providing mutually orthogonal outputs; means connected to the output of said phase detecting means for detecting phase and frequency errors between said modulated carrier wave and said reference phase signal, said phase and frequency error detecting means comprising n-stage multiplication means for multiplying said mutually orthogonal outputs of said phase detecting means, the nth stage of said n-stage multiplication means having first and second inputs, delay means having an input coupled to the first input of said nth stage for delaying said first input of said nth stage of said n-stage multiplication means by a predetermined time, one-stage multiplication means for multiplying the second input of said nth stage by the output of said delay means, and means for voltage-comparing the output of said n-stage multiplication means with that of said one-stage multiplication means to cancel said phase error contained in the outputs of said n-stage multiplication means and one-stage multiplication means; and means for supplying the outputs of said phase and frequency error detecting means to said voltage-controlled oscillator as said control signal.
Claim 2
Dependent Claim
236 words
A phase locked loop circuit comprising: a voltage-controlled oscillator for generating a reference phase signal in response to a control signal; phase detecting means for receiving an N-phase (N=2 n , n is a positive integer) phase-modulated carrier wave and said reference phase signal and for detecting said carrier wave on the basis of said reference phase signal, said phase detecting means providing mutually orthogonal outputs; means connected to the output of said phase detecting means for detecting phase and frequency errors between said modulated carrier wave and said reference phase signal, said phase and frequency error detecting means comprising n-stage multiplication means for multiplying said mutually orthogonal outputs of said phase detecting means, the nth stage of said n-stage multiplication means having first and second inputs, delay means having an input coupled to the first input of said nth stage for delaying said first input of said nth stage of said n-stage multiplication means by a predetermined time, one-stage multiplication means for multiplying the second input of said nth stage by the output of said delay means, and means for voltage-comparing the output of said n-stage multiplication means with that of said one-stage multiplication means to cancel said phase error contained in the outputs of said n-stage multiplication means and one-stage multiplication means; and means for supplying the outputs of said phase and frequency error detecting means to said voltage-controlled oscillator as said control signal.
Claim 3
Dependent Claim
185 words
A phase locked loop circuit comprising: a voltage-controlled oscillator for generating reference phase signal in response to a control signal, phase detecting means for receiving an N-phase (N=2 n , n is a positive integer) phase-modulated carrier wave and said reference phase signal and for phase-detecting said carrier on the basis of said reference phase signal, first detecting means connected to the output of said phase detecting means and that of said voltage-controlled oscillator for detecting a phase error between said modulated carrier signal and said reference phase signal, second detecting means connected to the output of said phase detecting means and that of the said voltage-controlled oscillator for detecting a frequency error and said phase error between said modulated carrier signal and said reference phase signal, means for voltage-comparing the output of said first detecting means with that of second detecting means to cancel said phase errors contained in the outputs of said first and second detecting means, and means for supplying the outputs of said first detecting means and that of the said voltage-comparing means to said voltage-controlled oscillator as said control signal.
Claim 4
Dependent Claim
185 words
A phase locked loop circuit comprising: a voltage-controlled oscillator for generating reference phase signal in response to a control signal, phase detecting means for receiving an N-phase (N=2 n , n is a positive integer) phase-modulated carrier wave and said reference phase signal and for phase-detecting said carrier on the basis of said reference phase signal, first detecting means connected to the output of said phase detecting means and that of said voltage-controlled oscillator for detecting a phase error between said modulated carrier signal and said reference phase signal, second detecting means connected to the output of said phase detecting means and that of the said voltage-controlled oscillator for detecting a frequency error and said phase error between said modulated carrier signal and said reference phase signal, means for voltage-comparing the output of said first detecting means with that of second detecting means to cancel said phase errors contained in the outputs of said first and second detecting means, and means for supplying the outputs of said first detecting means and that of the said voltage-comparing means to said voltage-controlled oscillator as said control signal.
Claim 5
Dependent Claim
76 words
A phase locked loop circuit as claimed in claim 2, in which said first detecting means comprises a first phase comparison means for phase-comparing the output of said phase detecting means with that of said voltage-controlled oscillator; and said second detecting means comprises means for delaying the output of said voltage-controlled oscillator by a predetermined time, and second phase comparison means for phase-comparing the output of said phase detecting means with that of said delay means.
Claim 6
Dependent Claim
21 words
A phase locked loop circuit as claimed in claim 1 or 2, in which said voltage-comparing means comprises a differential amplifier.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-07-05 | 1986-01-04 | 1986-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-07-05 | 1990-01-04 | 1990-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-07-05 | 1994-01-04 | 1994-07-06 | $7700.00 | Window Closed / Lapsed |