Transistorized focal plane having floating gate output nodes

Claim 2

A focal plane array, comprising: a semiconductive substrate; a plurality of photodetectors formed on said semiconductive substrate; a plurality of transistorized output circuits formed on said substrate, each of said output circuits comprising at least one metal oxide semiconductor field effect transistor formed on said semiconductive substrate adjacent a corresponding one of said detectors, a floating output node connected to said transistor and said corresponding one detector, means for periodically resetting the potential of said floating node, and a voltage output terminal having a voltage at least periodically determined by the corresponding one of said detectors.

Claim 3

The device of claim 1 further comprising a row enable transistor connected between the drain of said source follower transistor and a row enable line, and a reset transistor connected between the gate of said source follower transistor and a reset line.

Claim 4

The device of claim 1 wherein said source follower transistor includes a gate electrode, said floating node being connected to said gate electrode.

Claim 5

The device of claim 1 further comprising means for selectively resetting said floating node and enabling said source follower transistor.

Claim 6

An integrated transistorized imager, comprising: a semiconductor substrate; a plurality of photodetector diodes formed in said substrate and organized by row and column; a plurality of row enable lines associated with corresponding ones of said rows; a plurality of column output lines associated with corresponding ones of said columns; a plurality of output circuits associated with corresponding ones of said detectors, each of said output circuits comprising: a field effect transistor formed on said substrate adjacent a corresponding detector, said transistor comprising a source, a drain and a gate, said gate connected to said detector; means connected to the corresponding one of said row enable lines for at least periodically connecting the drain of said transistor to a drain voltage source; and means connected to said one row enable line and connected to receive a reset clock signal for periodically resetting the potential of said transistor gate.

Claim 7

An integrated transistorized imager, comprising: a semiconductor substrate; a plurality of photodetector diodes formed in said substrate and organized by row and column; a plurality of row enable lines associated with corresponding ones of said rows; a plurality of column output lines associated with corresponding ones of said columns; a plurality of output circuits associated with corresponding ones of said detectors, each of said output circuits comprising: a field effect transistor formed on said substrate adjacent a corresponding detector, said transistor comprising a source, a drain and a gate, said gate connected to said detector; means connected to the corresponding one of said row enable lines for at least periodically connecting the drain of said transistor to a drain voltage source; and means connected to said one row enable line and connected to receive a reset clock signal for periodically resetting the potential of said transistor gate.

Claim 8

The device of claim 5 wherein said connecting means comprises an enable transistor formed on said semiconductor substrate adjacent said field effect transistor, said enable transistor having its own source, drain and gate, said enable transistor source connected to said field effect transistor gate and said enable transistor drain connected to said drain voltage source, the gate of said enable transistor connected to the corresponding one of said row enable lines.

Claim 9

The device of claim 6 wherein said resetting means comprise a dual gate transistor formed on said semiconductive substrate having two gates and a source and a drain, one of said two gates being connected to receive a periodic clock signal φ rst and the other of said gates connected to the corresponding one of said row enable lines, said reset transistor source being connected to said field effect transistor gate, and said drain of said reset transistor being connected to a reset voltage source.

Claim 10

The device of claim 5 wherein said field effect transistor comprises a source follower transistor.

Claim 11

The device of claim 8 wherein said field effect transistor comprises an inverter.