US4442748A — Frequency divider for electronic musical instrume…

Claim 1

Independent Claim 205 words

A frequency divider for use in an electronic musical instrument comprising: counter means driven by a predetermined clock pulse for producing a plural-bit count output, said count output having a certain number of different possible values; cycle data forming means for forming, for each value of count output from said counter means, a certain plural-bit cycle data value in which only a specific single bit is in a first binary state and the rest of the bits are in a second binary state, whereby a certain cycle data value is formed for selected ones of said certain number of different count output possible values, the ratio of the number of cycle data values having a particular specific single bit in a first binary state to the total number of possible different count output values being proportional to the binary significance of said particular certain single bit; and inhibit means for comparing a plural-bit dividing ratio data representative of a dividing ratio with said cycle data for every corresponding bit and for inhibiting counting operation of said counter means when corresponding bits of said dividing ratio data and said cycle data are first states, whereby dividing data is obtained from the output from said counter means.

Claim 2

Dependent Claim 205 words

A frequency divider for use in an electronic musical instrument comprising: counter means driven by a predetermined clock pulse for producing a plural-bit count output, said count output having a certain number of different possible values; cycle data forming means for forming, for each value of count output from said counter means, a certain plural-bit cycle data value in which only a specific single bit is in a first binary state and the rest of the bits are in a second binary state, whereby a certain cycle data value is formed for selected ones of said certain number of different count output possible values, the ratio of the number of cycle data values having a particular specific single bit in a first binary state to the total number of possible different count output values being proportional to the binary significance of said particular certain single bit; and inhibit means for comparing a plural-bit dividing ratio data representative of a dividing ratio with said cycle data for every corresponding bit and for inhibiting counting operation of said counter means when corresponding bits of said dividing ratio data and said cycle data are first states, whereby dividing data is obtained from the output from said counter means.

Claim 3

Dependent Claim 45 words

The frequency divider of claim 1 wherein said first binary state is binary 1, said second binary state is binary 0, and said certain number of different possible count output values is 2 n where n is the number of bits of said count output.

Claim 4

Dependent Claim 37 words

A frequency divider as defined in claim 2, wherein said counter means includes a plurality of plural-bit addition circuits connected to each other in series, and said cycle data forming means includes a plurality of AND gates.

Claim 5

Dependent Claim 51 words

A frequency divider as defined in claim 3 wherein each of said addition circuits includes a carry input for receiving a carry input signal and an output for an addition output signal and said AND gates perform the logical AND function on said carry input signal and said addition output signal.

Claim 6

Dependent Claim 37 words

A frequency divider as defined in claim 4, wherein each of said addition circuits adds the prior contents of said each addition circuit to a signal fed into the carry input thereof synchronized with said clock pulse.

Claim 7

Dependent Claim 87 words

A frequency divider as defined in claim 1, wherein said cycle data forming means includes: a plurality of delay flip-flops for respectively delaying the output of said counter means for each bit; a plurality of EXCLUSIVE-OR gates for respectively performing EXCLUSIVE-OR operation on the output of said delay flip-flop circuit and the output of said counter means for each bit; and a plurality of AND gates for performing AND operation on the output of said EXCLUSIVE-OR gate and the output of said counter means for each bit.

Claim 8

Dependent Claim 107 words

A frequency divider as defined in claim 1, wherein said cycle data forming means includes: a plurality of AND gates provided corresponding to each bit of said counter means except the least significant bit, one input and said AND gates respectively receiving the output of said counter means for each bit except the least significant bit; and a plurality of INVERTER gates provided corresponding to each bit of said counter means except the most significant bit for inverting the output of said each bit so as to feed the inverted output into the other input of said AND gate of one bit higher than said each bit.

Claim 9

Dependent Claim 73 words

A frequency divider as defined in claim 1, wherein said inhibit means includes a plurality of AND gates for performing AND operation on said dividing ratio data and said cycle data with respect to each corresponding bit thereof; an OR gate for performing OR operation on the output of said AND gates; and a suspension circuit for suspending counting operation of said counter means in response to the output of said OR gate.

Claim 10

Dependent Claim 41 words

A frequency divider as defined in claim 8, wherein said suspension circuit is a circuit for inhibiting the carry input signal from feeding into the carry input of said addition circuit corresponding to the least significant bit of said counter means.

Claim 11

Dependent Claim 159 words

A frequency divider for producing polyphonic sounds in an electronic musical instrument comprising: a counter comprising a plurality of addition circuits connected to each other in series, a plurality of first N-stage shift registers respectively provided corresponding to each of said addition, circuits for supplying output signals of said addition circuits to an input thereof after delaying said output signals by N clock cycles, N being a positive integer larger than 1, means for generating N dividing ratio data bite inhibit means for outputting an inhibit signal when a carry input signal and the corresponding output signal of at least one of said addition circuits and a bit corresponding to said one of said addition circuits of said dividing ratio data are all logically 1, and a second N-stage shift register provided between said inhibit means and said counter for supplying said inhibit signal into an input of said counter so as to suspend counter operation of said counter.

Claim 12

Dependent Claim 159 words

A frequency divider for producing polyphonic sounds in an electronic musical instrument comprising: a counter comprising a plurality of addition circuits connected to each other in series, a plurality of first N-stage shift registers respectively provided corresponding to each of said addition, circuits for supplying output signals of said addition circuits to an input thereof after delaying said output signals by N clock cycles, N being a positive integer larger than 1, means for generating N dividing ratio data bite inhibit means for outputting an inhibit signal when a carry input signal and the corresponding output signal of at least one of said addition circuits and a bit corresponding to said one of said addition circuits of said dividing ratio data are all logically 1, and a second N-stage shift register provided between said inhibit means and said counter for supplying said inhibit signal into an input of said counter so as to suspend counter operation of said counter.

Claim 13

Independent Claim 126 words

The method of dividing the frequency of a high frequency clock signal including the steps: counting the pulses from a predetermined high frequency clock signal to form a binary count output for each counting step; forming plural bit cycle data from each binary count output such that said cycle data has only one bit at binary value 1 and the ratio at which each bit becomes binary value 1 over several successive binary count outputs is proportional to the significance of said bit; comparing each bit of said cycle data with each corresponding bit of externally input dividing ratio data; inhibiting said counting operation for at least one counting step when said cycle data and said dividing ratio data have corresponding bits at logic level 1.

Claim 14

Independent Claim 126 words

The method of dividing the frequency of a high frequency clock signal including the steps: counting the pulses from a predetermined high frequency clock signal to form a binary count output for each counting step; forming plural bit cycle data from each binary count output such that said cycle data has only one bit at binary value 1 and the ratio at which each bit becomes binary value 1 over several successive binary count outputs is proportional to the significance of said bit; comparing each bit of said cycle data with each corresponding bit of externally input dividing ratio data; inhibiting said counting operation for at least one counting step when said cycle data and said dividing ratio data have corresponding bits at logic level 1.

Claim 15

Dependent Claim 42 words

The method of claim 11 wherein the set of steps of counting, forming, comparing, and inhibiting is performed separately on a plurality of channels on a time division multiplex basis to provide a different frequency for each of said plurality of channels.

Claim 16

Dependent Claim 245 words

An electronic musical instrument comprising: a keyboard circuit having a plurality of keyswitches for producing a key code corresponding to an operated keyswitch, a dividing ratio data memory for storing a dividing ratio data corresponding to said key code, a frequency divider for producing a frequency divided data corresponding to said dividing ratio data, said frequency divider comprising: counter means driven by a predetermined clock pulse for producing a plural-bit count output, said count output having a certain number of different possible values; cycle data forming means for forming, for each value of count output from said counter means, a certain plural-bit cycle data value in which only a specific single bit is in a first binary state and the rest of the bits are in a second binary state, whereby a certain cycle data value is formed for selected ones of said certain number of different count output possible values, the ratio of the number of cycle data values having a particular specific single bit in a first binary state to the total number of possible different count output values being proportional to the binary significance of said particular certain single bit; and inhibit means for inhibiting counting operation of said counter means when corresponding bits of said dividing ratio data and said cycle data are the first state, and a sound system for forming a musical tone signal in response to output of said frequency divider so as to produce a musical tone.

Claim 17

Dependent Claim 245 words

An electronic musical instrument comprising: a keyboard circuit having a plurality of keyswitches for producing a key code corresponding to an operated keyswitch, a dividing ratio data memory for storing a dividing ratio data corresponding to said key code, a frequency divider for producing a frequency divided data corresponding to said dividing ratio data, said frequency divider comprising: counter means driven by a predetermined clock pulse for producing a plural-bit count output, said count output having a certain number of different possible values; cycle data forming means for forming, for each value of count output from said counter means, a certain plural-bit cycle data value in which only a specific single bit is in a first binary state and the rest of the bits are in a second binary state, whereby a certain cycle data value is formed for selected ones of said certain number of different count output possible values, the ratio of the number of cycle data values having a particular specific single bit in a first binary state to the total number of possible different count output values being proportional to the binary significance of said particular certain single bit; and inhibit means for inhibiting counting operation of said counter means when corresponding bits of said dividing ratio data and said cycle data are the first state, and a sound system for forming a musical tone signal in response to output of said frequency divider so as to produce a musical tone.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1987-04-17	1987-10-17	1988-04-17	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1991-04-17	1991-10-17	1992-04-17	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1995-04-17	1995-10-17	1996-04-17	$7700.00	Window Closed / Lapsed

Frequency divider for electronic musical instrument

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