US4441037A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Internally gated variable pulsewidth clock generator
Assignee: Unisys Corp
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Filing: 1980-12-22
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Granted: 1984-04-03
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Expires: 2000-12-22
Abstract
Abstract This disclosure relates to a variable pulsewidth gated clock generator which is able to provide output clock signals with the same rise rate as an external driving clock with the output signal being varied in duration according to logic conditions within the integrated circuit. The circuit of the present invention as disclosed includes a latch which is set by the first phase of a two-phase clock to set the internal logic of the circuit to generate a large output signal during the second phase of the two-phase clock.
Inventors
- 👤 Gregory E. Gaertner
- 👤 Ta-Ming Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:21
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023; G; G09; G09G; G09G5/00; G09G5/18; H03K5/04; H03K5/05
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
170 words
A circuit apparatus for generating a variable pulsewidth high ramp rate output signal in response to a pair of complementary clock signals and a logic signal, said generator comprising: a first transistor means disposed for gating therethrough said logic signal in response to a first of said pair of clock signals; latch circuit means having an input terminal coupled to said first transistor means and having an output terminal; second transistor means having a gate terminal coupled to said output terminal of said latch circuit means and a first signal terminal coupled to a second of said pair of clock signals; third transistor means having a gate terminal coupled to the second signal terminal of said second transistor, a first signal terminal coupled to said second of said pair of clock signals and a second signal terminal coupled to an output terminal of said circuit apparatus, such that the ramp rate of said output signal is equal to the ramp rate of said second of said pair of clock signals.
Claim 2
Dependent Claim
170 words
A circuit apparatus for generating a variable pulsewidth high ramp rate output signal in response to a pair of complementary clock signals and a logic signal, said generator comprising: a first transistor means disposed for gating therethrough said logic signal in response to a first of said pair of clock signals; latch circuit means having an input terminal coupled to said first transistor means and having an output terminal; second transistor means having a gate terminal coupled to said output terminal of said latch circuit means and a first signal terminal coupled to a second of said pair of clock signals; third transistor means having a gate terminal coupled to the second signal terminal of said second transistor, a first signal terminal coupled to said second of said pair of clock signals and a second signal terminal coupled to an output terminal of said circuit apparatus, such that the ramp rate of said output signal is equal to the ramp rate of said second of said pair of clock signals.
Claim 3
Dependent Claim
25 words
A circuit apparatus as in claim 1 further characterized by said second transistor means having a relatively small capacitance for providing a first switching characteristic.
Claim 4
Dependent Claim
24 words
A circuit apparatus as in claim 1 further characterized by said third transistor means having a relatively large capacitance for providing said output signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-04-03 | 1987-10-03 | 1988-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-04-03 | 1991-10-03 | 1992-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-04-03 | 1995-10-03 | 1996-04-03 | $7700.00 | Window Closed / Lapsed |