Method and apparatus for verifying storage apparatus addressing

Claim 2

The machine-implemented method of operating a volatile random access data storage unit including a first plurality of addressable data storage registers; the steps of: allocating said first plurality of addressable registers into a second plurality smaller than said first plurality of groups of said addressable registers, each group having a given number of said addressable registers; addressing each of said groups of addressable registers as a single group and accessing individual ones of said addressable registers in said group in a predetermined sequence including all but a last one of said addressable registers that would be next accessed by any reference to said data storage unit; initializing the signal state of all said last one addressable registers in a given reference state; and before accessing said addressable registers in said data storage unit, presetting an address for a group to be accessed for enabling said predetermined sequence such that said last one addressable registers are never normally accessed whereby any access to said one addressable registers indicates one error condition.

Claim 3

The machine-implemented method set forth in claim 1 further including the machine-executable steps of: storing data signals in a one of said groups and including error detection signals as a part of said stored data signals; and storing said error detection signals in a second one of said addressable registers to be accessed in said predetermined sequence as the address immediately preceding said last one addressable register.

Claim 4

The machine-implemented method set forth in claim 1 or 2, further including the steps of: storing on error detection set of signals in each said group of addressable registers for data signals stored therein; transferring data signals between said data storage unit and another unit and generating a second error detection set of signals for data signals transferred with a given one of said groups of addressable registers; reading said stored error detection set of signals from said given group of addressable registers and comparing same with said second error detection set of signals; and upon a miscompare signal an error condition.

Claim 5

A volatile data storage unit including an error-checking arrangement and having a plurality of addressable data storage registers; comprising: means coupled to said plurality of addressable data storage registers for indicating allocated numbers of said addressable registers as allocation groups of said addressable registers which occupy a given range of addresses identifying corresponding ones of said addressable registers in respective ones of said groups; means coupled to said plurality of addressable data storage registers for receiving two of said addressable registers at one end of said range of addresses in each of said groups for non-data control, an ultimate one of said two registers corresponding to a last address of said range in each of said groups and for containing reference signals and a penultimate one of said two registers corresponding to a penultimate address of said range in each of said groups for containing error detection signals relating to data signals stored in said addressable registers in said respective group; and addressing means coupled to said means for indicating and to said plurality of addressable data storage registers for addressing said addressable registers including means normally preventing addressing said ultimate register after given accesses to said addressable register.

Claim 6

A volatile data storage unit including an error-checking arrangement and having a plurality of addressable data storage registers; comprising: means coupled to said plurality of addressable data storage registers for indicating allocated numbers of said addressable registers as allocation groups of said addressable registers which occupy a given range of addresses identifying corresponding ones of said addressable registers in respective ones of said groups; means coupled to said plurality of addressable data storage registers for receiving two of said addressable registers at one end of said range of addresses in each of said groups for non-data control, an ultimate one of said two registers corresponding to a last address of said range in each of said groups and for containing reference signals and a penultimate one of said two registers corresponding to a penultimate address of said range in each of said groups for containing error detection signals relating to data signals stored in said addressable registers in said respective group; and addressing means coupled to said means for indicating and to said plurality of addressable data storage registers for addressing said addressable registers including means normally preventing addressing said ultimate register after given accesses to said addressable register.

Claim 7

A data storage apparatus having a settable address counter capable of addressing a first plurality of addressable registers in the data storage apparatus; the improvement including in combination; allocation means coupled to said first plurality of addressable registers and to said address counter for establishing a data addressing map of a second plurality less than said first plurality of groups of said addressable registers, all registers in each group being addressable in a sequence of consecutive addresses counted in said address counter; means coupled to said address counter for cycling said address counter through said sequence of consecutive addresses; means coupled to said address counter for forcing said address counter to contain an address at the end of each of said sequences of consecutive addresses from an address of a first addressable register in a contiguously addressed group of said addressable register such that failure to set said address counter prior to accessing registers of the data storage apparatus results in an unintended sequence of accesses to said addressable registers not in congruence with said groups; and means coupled to said address counter and said coupled means for detecting said unintended sequence and having further means for being responsive to said unintended sequence to indicate an error condition.

Claim 8

A data storage apparatus having a settable address counter capable of addressing a first plurality of addressable registers in the data storage apparatus; the improvement including in combination; allocation means coupled to said first plurality of addressable registers and to said address counter for establishing a data addressing map of a second plurality less than said first plurality of groups of said addressable registers, all registers in each group being addressable in a sequence of consecutive addresses counted in said address counter; means coupled to said address counter for cycling said address counter through said sequence of consecutive addresses; means coupled to said address counter for forcing said address counter to contain an address at the end of each of said sequences of consecutive addresses from an address of a first addressable register in a contiguously addressed group of said addressable register such that failure to set said address counter prior to accessing registers of the data storage apparatus results in an unintended sequence of accesses to said addressable registers not in congruence with said groups; and means coupled to said address counter and said coupled means for detecting said unintended sequence and having further means for being responsive to said unintended sequence to indicate an error condition.

Claim 9

The machine-implemented method of operating a volatile random-access storage apparatus having a first plurality of addressable data-storage registers; the automatic steps of: allocating said first plurality of addressable data-storage registers into a second plurality less than said first plurality of addressable groups of said registers in accordance with a given allocation map of addresses; accessing by activating addressing means to address said addressable data storage registers in each of said groups in a sequence of consecutive addresses such that all of said addressable data storage registers for containing data signals are accessed as a single group; upon completion of each said accessing inducing an address offset in said addressing means such that any next access to said addressable data-storage registers without setting a new address into said addressing means results in accessing ones of said addressable data-storage registers which are incongruent with said allocation map; and detecting and indicating said incongruence as an error condition.

Claim 10

The machine-implemented method of operating a volatile random-access storage apparatus having a first plurality of addressable data-storage registers; the automatic steps of: allocating said first plurality of addressable data-storage registers into a second plurality less than said first plurality of addressable groups of said registers in accordance with a given allocation map of addresses; accessing by activating addressing means to address said addressable data storage registers in each of said groups in a sequence of consecutive addresses such that all of said addressable data storage registers for containing data signals are accessed as a single group; upon completion of each said accessing inducing an address offset in said addressing means such that any next access to said addressable data-storage registers without setting a new address into said addressing means results in accessing ones of said addressable data-storage registers which are incongruent with said allocation map; and detecting and indicating said incongruence as an error condition.

Claim 11

Data processing apparatus including storage (10) accessed by a continuous spectrum of physical addresses, each address being for a respective addressable data storage location and a processing system (14) operative in a corresponding continuous spectrum of system addresses and a mechanism for mapping system addresses by block into physical addresses by block and into corresponding system addresses by block; characterized in that: as a fault detection indicator, for each block of addresses, the physical block capacity of addressable data storage locations is greater than its system block capacity of addressable data storage locations and that the excess of the addressable data storage locations lies at that end of each such block reached last under an address indexing operation of the system.

Claim 12

Data processing apparatus including storage (10) accessed by a continuous spectrum of physical addresses, each address being for a respective addressable data storage location and a processing system (14) operative in a corresponding continuous spectrum of system addresses and a mechanism for mapping system addresses by block into physical addresses by block and into corresponding system addresses by block; characterized in that: as a fault detection indicator, for each block of addresses, the physical block capacity of addressable data storage locations is greater than its system block capacity of addressable data storage locations and that the excess of the addressable data storage locations lies at that end of each such block reached last under an address indexing operation of the system.

Claim 13

Apparatus as claimed in claim 7 wherein each said excess is zeroed.

Claim 14

Apparatus as claimed in claim 8 wherein each said excess stores detectable control information.

Claim 15

Apparatus as claimed in claim 7 including an error code generator and detector, said excess having two addressable locations per block arranged to generate on writing an error code word for the block and load the same into the first of the two excess locations, the second of the two excess locations containing either detectable control information or being maintained empty.

Claim 16

Apparatus as claimed in claim 10 in which each stored block includes error-indicating redundancy, the arrangement being such that, on reading, the redundancy said block is compared with the excess location error word.