← Back to Patent Explorer
US4438393A Expired / Lapsed US ⏱️ 0.0 years remaining

Phase-metering device

Assignee: Individual
•
Filing: 1981-08-18
•
Granted: 1984-03-20
•
Expires: 2001-08-18
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A phase-metering device comprises first and second input signal sources; N-1 phase-shift circuits at N exceeding two, which are placed in series, a phase shift of each of said circuits being equal to π/N radians, the input of the first phase-shifter circuit being connected to the second input signal source; N phase converter units each having two potential (positive and inverted) outputs and two pulse outputs, first inputs of said units being connected to the first input signal source, a second input of the first phase converter unit being connected to the first input signal source, while second inputs of the other phase converter units are coupled to the outputs of the respective phase-shift circuits; the outputs of said phase converter units being connected to inputs of a pulse distributor whose outputs are coupled to inputs of a reversible counter; a digital recorder being connected to the outputs of said reversible counter.

Inventors

  • 👤 Leonid M. Moskalik
  • 👤 Vladimir E. Ryadchikov
  • 👤 Anatoly P. Bykov
  • 👤 Vladimir P. Kulesh
  • 👤 Stanislav I. Opasov
  • 👤 Anatoly A. Orlov

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 20:26
CPC Classifications
G; G01; G01R; G01R25/00; H; H03; H03K; H03K5/00; H03K5/153; H03K5/1532; H03K5/22; H03K5/26

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 150 words
A phase-metering device comprising: first and second input signal source; N-1 phase-shift circuits at N exceeding two and a phase-shift of each circuit being π/N radians, said N-1 phase-shift circuits being electrically-connected in series, an input of the first circuit being connected to the second input signal source; N phase converter units each having positive and inverted outputs and two pulse outputs, first inputs of said units being connected to the first input signal source, a second input of the first phase converter unit being coupled to the second input signal source, while second inputs of the other phase converter units are connected to the outputs of the respective phase-shift circuits; a pulse distributor whose inputs are connected to outputs of said phase converter units; a reversible counter whose inuts are connected to the outputs of said pulse distributor; a digital recorder coupled to the outputs of said reversible counter.
Claim 2
Dependent Claim 150 words
A phase-metering device comprising: first and second input signal source; N-1 phase-shift circuits at N exceeding two and a phase-shift of each circuit being π/N radians, said N-1 phase-shift circuits being electrically-connected in series, an input of the first circuit being connected to the second input signal source; N phase converter units each having positive and inverted outputs and two pulse outputs, first inputs of said units being connected to the first input signal source, a second input of the first phase converter unit being coupled to the second input signal source, while second inputs of the other phase converter units are connected to the outputs of the respective phase-shift circuits; a pulse distributor whose inputs are connected to outputs of said phase converter units; a reversible counter whose inuts are connected to the outputs of said pulse distributor; a digital recorder coupled to the outputs of said reversible counter.
Claim 3
Dependent Claim 172 words
A phase-metering device as claimed in claim 1, which is provided with a sign recorder inserted between said pulse distributor and said reversible counter having a null indicator, said sign recorder having a sign flip-flop -flop, two NAND gates, two two-input AND-OR gates and four AND gates whose first inputs are connected to the outputs of said pulse distributor, the outputs of the first two AND gates being connected to the inputs of said sign flip-flop whose outputs are connected to the first inputs of said NAND gates and to the inputs if said two-input AND-OR gates connected in pairs, the outputs of said NAND gates being coupled to the second inputs of the two AND gates whose outputs are connected to the other inputs of said two-input AND-OR gates connected in pairs, the outputs of said two-input AND-OR gates being coupled to the inputs of said reversible counter, while the second inputs of said NAND gates and the first two AND gates are coupled to the output of said null indicator.
Claim 4
Dependent Claim 90 words
A phase-metering device as claimed in claim 1, which comprises a code converter placed between said potential outputs of said phase converter units and the inputs of lower-order digit inputs of the digital recorder, while said pulse distributor includes two AND gates, whose first inputs are coupled to said pulse outputs of the last phase converter unit, second inputs thereof being interconnected and coupled to one of the potential outputs of one of the preceding phase converter units, while the outputs thereof act as the outputs of said pulse distributor.
Claim 5
Dependent Claim 121 words
A phase-metering device as claimed in claim 3, wherein at N=4 and a binary count and recording system said code converter includes three exclusive OR gates, inputs of the first gate being connected to said positive potential outputs of the second and fourth phase converter units, inputs of said second exclusive OR gate being coupled to said positive potential outputs of the first and third phase converter units, while inputs of the third exclusive OR gate is coupled to the outputs of the first two exclusive OR gates, said positive potential output of said fourth phase converter unit and the outputs of the first and third exclusive OR gates are connected to the lower-order digit inputs of the said digital recorder.

References Cited (Backward Citations)

US3820022A Cited
US4144489A Cited
US3989931A Cited
US4070618A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-03-20 1987-09-19 1988-03-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-03-20 1991-09-19 1992-03-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-03-20 1995-09-19 1996-03-20 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag