Patent US4776074A successfully refreshed from Google Patents.
Patent US4437086A successfully refreshed from Google Patents.
US4437086A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Limited look-ahead means
Assignee: Ampex Corp
•
Filing: 1980-03-17
•
Granted: 1984-03-13
•
Expires: 2000-03-17
Abstract
Abstract A method and apparatus provide for the elimination of any net DC component from the transmission of binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states, e.g., 0's, are normally transmitted as signal transitions relatively early in respective bit cells, preferably at cell edge, and logical second bit states, e.g., 1's, are normally transmitted as signal transitions relatively late in respective bit cells, preferably at mid-cell, and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed. The onset of a sequence of second bit states following a first bit state that might introduce a DC component into the transmitted signal with normal transmission is detected by counting first bit states and producing a first indicating signal when the count is of parity indicating such sequence, and in response to the first indicating signal, a current bit and an adjacent bit the transmission of signal transitions is modified from the onset of such sequence to eliminate any DC component. Preferably, the possibly troublesome sequences are encoded by encoding pairs of second bit states by a single transition early in the first bit cell of the pair. Further, a limited look-ahead means is provided which is responsive to the first indicating signal, a current bit and a limited number of next succeeding bits for producing a disabling signal at the onset of any such sequence that terminates within the limited number of next succeeding bits and would not introduce such DC component with normal transmission. In addition, means responsive to the disabling signal is provided for disabling the transition modifying means for the transmission of signal transitions corresponding to all of the second bit states of such sequence that would not introduce such DC component with normal transmission.
Inventors
- 👤 Jerry W. Miller
- 👤 Paul J. Rudnick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:21
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423; H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4906
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
290 words
In a self-clocking transmission system for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed, apparatus for modifying the transmitted signal to remove any net DC component, said apparatus comprising first indicating means responsive to first bit states for counting the number of first bit states and producing at the onset of a sequence of second bit states following a first bit state a first indicating signal when the number of first bit states is of predetermined parity indicating any such sequence that might introduce a DC component into the transmitted signal with normal transmission, transition modifying means responsive to said first indicating signal, a current bit of such sequence and an adjacent bit for modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component, limited look-ahead means responsive to said first indicating signal, a current bit and a limited number greater than two of next succeeding bits for producing a disabling signal at the onset of any such sequence that terminates within said limited number of next succeeding bits and would not introduce such DC component with normal transmission, and means responsive to said disabling signal for disabling said transition modifying means for the transmission of signal transitions corresponding to all of the second bit states of such sequence that would not introduce such DC component with normal transmission.
Claim 2
Dependent Claim
290 words
In a self-clocking transmission system for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed, apparatus for modifying the transmitted signal to remove any net DC component, said apparatus comprising first indicating means responsive to first bit states for counting the number of first bit states and producing at the onset of a sequence of second bit states following a first bit state a first indicating signal when the number of first bit states is of predetermined parity indicating any such sequence that might introduce a DC component into the transmitted signal with normal transmission, transition modifying means responsive to said first indicating signal, a current bit of such sequence and an adjacent bit for modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component, limited look-ahead means responsive to said first indicating signal, a current bit and a limited number greater than two of next succeeding bits for producing a disabling signal at the onset of any such sequence that terminates within said limited number of next succeeding bits and would not introduce such DC component with normal transmission, and means responsive to said disabling signal for disabling said transition modifying means for the transmission of signal transitions corresponding to all of the second bit states of such sequence that would not introduce such DC component with normal transmission.
Claim 3
Dependent Claim
63 words
Apparatus in accordance with claim 1 wherein said transition modifying means modifies the transmission of signal transitions to provide a single transition corresponding to each pair of second bit states of such sequence where the first of the pair is an odd second bit state, which single transition is transmitted relatively early in the respective bit cell for the first of the pair.
Claim 4
Dependent Claim
326 words
In a self-clocking transmission system for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in the respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed, apparatus for modifying the transmitted signal to remove any net DC component, said apparatus comprising first indicating means responsive to first bit states for counting the number of first bit states and producing at the onset of a sequence of second bit states following a first bit state a first indicating signal when the number of first bit states is of predetermined parity indicating any such sequence that might introduce a DC component into the transmitted signal with normal transmission, second indicating means responsive to bit states for producing a second indicating signal indicating whether the number of second bit states occurring in such sequence prior to a current bit is odd or even, transition modifying means responsive to said first and second indicating signals and to the current bit and an adjacent bit for modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component, limited look-ahead means responsive to said first indicating signal, a current bit and a limited number greater than two of next succeeding bits for producing a disabling signal at the onset of any such sequence that terminates within said limited number of next succeeding bits and would not introduce such DC component with normal transmission, and means responsive to said disabling signal for disabling said transition modifying means for the transmission of signal transitions corresponding to all of the second bit states of such sequence that would not introduce such DC component with normal transmission.
Claim 5
Dependent Claim
326 words
In a self-clocking transmission system for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in the respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed, apparatus for modifying the transmitted signal to remove any net DC component, said apparatus comprising first indicating means responsive to first bit states for counting the number of first bit states and producing at the onset of a sequence of second bit states following a first bit state a first indicating signal when the number of first bit states is of predetermined parity indicating any such sequence that might introduce a DC component into the transmitted signal with normal transmission, second indicating means responsive to bit states for producing a second indicating signal indicating whether the number of second bit states occurring in such sequence prior to a current bit is odd or even, transition modifying means responsive to said first and second indicating signals and to the current bit and an adjacent bit for modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component, limited look-ahead means responsive to said first indicating signal, a current bit and a limited number greater than two of next succeeding bits for producing a disabling signal at the onset of any such sequence that terminates within said limited number of next succeeding bits and would not introduce such DC component with normal transmission, and means responsive to said disabling signal for disabling said transition modifying means for the transmission of signal transitions corresponding to all of the second bit states of such sequence that would not introduce such DC component with normal transmission.
Claim 6
Dependent Claim
63 words
Apparatus in accordance with claim 3 wherein said transition modifying means modifies the transmission of signal transitions to provide a single transition corresponding to each pair of second bit states of such sequence where the first of the pair is an odd second bit state, which single transition is transmitted relatively early in the respective bit cell for the first of the pair.
Claim 7
Dependent Claim
170 words
Apparatus in accordance with any one of claims 1 to 4 further including decoding means responsive to transmitted signal transitions for indicating the bit states of the binary data transmitted, said decoding means comprising synchronizing means responsive to transmitted signal transitions for providing timing signals identifying bit cell intervals, detection means responsive to said transmitted signal transitions and said timing signals by producing transition identifying signals identifying received signal transitions as relatively early or relatively late in respective bit cells, and bit state recognition means responsive to said transition identifying signals by indicating a bit cell as being in the second bit state under any of the conditions of (a) a relatively late transition for the respective cell, (b) a relatively early transition for the respective cell where there is no transition for the next succeeding cell, and (c) no transition for the respective cell where there was no relatively late transition for the next preceding cell, and by indicating all other cells as being in the first bit state.
Claim 8
Dependent Claim
274 words
In a self-clocking method for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states of a sequence of data bit states are normally transmitted by signal transitions relatively early in respective bit cells and logical second bit states of said sequence of data bit states are normally transmitted as signal transitions relatively late in respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed, said method including generating a first indicating signal when the number of first bit states in the sequence of data bit states is of a predetermined parity, detecting the onset of a sequence of second bit states following a first bit state productive of said predetermined parity that might introduce a DC component into the transmitted signal with normal transmission, and in response to said first indicating signal, the state of a current bit and the state of an adjacent bit modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component, the improvement comprising in response to said first indicating signal examining a limited number greater than two of bits next succeeding a current bit to determine at the onset of any such sequence if the sequence terminates within said limited number of next succeeding bits and would not introduce such DC component with normal transmission, and inhibiting said modifying of the transmission of signal transitions corresponding to any of the second bit states of such sequence that would not introduce such DC component with normal transmission.
Claim 9
Dependent Claim
274 words
In a self-clocking method for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states of a sequence of data bit states are normally transmitted by signal transitions relatively early in respective bit cells and logical second bit states of said sequence of data bit states are normally transmitted as signal transitions relatively late in respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed, said method including generating a first indicating signal when the number of first bit states in the sequence of data bit states is of a predetermined parity, detecting the onset of a sequence of second bit states following a first bit state productive of said predetermined parity that might introduce a DC component into the transmitted signal with normal transmission, and in response to said first indicating signal, the state of a current bit and the state of an adjacent bit modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component, the improvement comprising in response to said first indicating signal examining a limited number greater than two of bits next succeeding a current bit to determine at the onset of any such sequence if the sequence terminates within said limited number of next succeeding bits and would not introduce such DC component with normal transmission, and inhibiting said modifying of the transmission of signal transitions corresponding to any of the second bit states of such sequence that would not introduce such DC component with normal transmission.
Claim 10
Dependent Claim
59 words
A method according to claim 6 wherein transmission of signal transitions is modified to produce a single transition corresponding to each pair of second bit states of such sequence when the first of the pair is an odd second bit state, which single transition is transmitted relatively early in the respective bit cell for the first of the pair.
Claim 11
Dependent Claim
291 words
In a self-clocking method for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states of a sequence of data bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states of said sequence of data bit states are normally transmitted as signal transitions relatively late in the respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed, said method including generating a first indicating signal when the number of first bit states in the sequence of data bit states is of a predetermined parity, detecting the onset of a sequence of second bit states following a first bit state productive of said predetermined parity that might introduce a DC component into the transmitted signal with normal transmission, generating a second indicating signal indicative of whether the number of second bit states in such sequence prior to a current bit is odd or even, and in response to said first and second indicating signals modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component, the improvement comprising in response to said first indicating signal examining a limited number greater than two of bits next succeeding a current bit to determine at the onset of any such sequence if the sequence terminates within said limited number of next succeeding bits and would not introduce such DC component with normal transmission, and inhibiting said modifying of the transmission of signal transitions corresponding to any of the second bit states of such sequence that would not introduce such DC component with normal transmission.
Claim 12
Dependent Claim
291 words
In a self-clocking method for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states of a sequence of data bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states of said sequence of data bit states are normally transmitted as signal transitions relatively late in the respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed, said method including generating a first indicating signal when the number of first bit states in the sequence of data bit states is of a predetermined parity, detecting the onset of a sequence of second bit states following a first bit state productive of said predetermined parity that might introduce a DC component into the transmitted signal with normal transmission, generating a second indicating signal indicative of whether the number of second bit states in such sequence prior to a current bit is odd or even, and in response to said first and second indicating signals modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component, the improvement comprising in response to said first indicating signal examining a limited number greater than two of bits next succeeding a current bit to determine at the onset of any such sequence if the sequence terminates within said limited number of next succeeding bits and would not introduce such DC component with normal transmission, and inhibiting said modifying of the transmission of signal transitions corresponding to any of the second bit states of such sequence that would not introduce such DC component with normal transmission.
Claim 13
Dependent Claim
59 words
A method according to claim 8 wherein transmission of signal transitions is modified to produce a single transition corresponding to each pair of second bit states of such sequence when the first of the pair is an odd second bit state, which single transition is transmitted relatively early in the respective bit cell for the first of the pair.
Claim 14
Independent Claim
131 words
A method according to any one of claims 6 to 9 wherein the transmitted signal is decoded by deriving timing signals from the transmitted data signal transition for identifying bit cell intervals, producing transitions identifying signals identifying received signal transitions as relatively early or relatively late in respective bit cells, and from said transition identifying signals indicating a bit cell as in the second bit state under any of the conditions of (a) a relatively late transition for the respective cell, (b) a relatively early transition for the respective cell where there is no transition for the next succeeding cell, and (c) no transition for the respective cell where there was no relatively late transition for the next preceding cell, all other cells being indicated as in the first bit state.
References Cited (Backward Citations)
US3108261A
Cited
US3564557A
Cited
US3623041A
Cited
US4001811A
Cited
US3810111A
Cited
US3995264A
Cited
US4027335A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-13 | 1987-09-12 | 1988-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-13 | 1991-09-12 | 1992-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-13 | 1995-09-12 | 1996-03-13 | $7700.00 | Window Closed / Lapsed |