US4435825A
Expired / Lapsed
US
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Clock signal extracting circuit
Assignee: Hitachi Ltd
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Filing: 1982-02-25
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Granted: 1984-03-06
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Expires: 2002-02-25
Abstract
Abstract A clock extractor is disclosed in which an input data signal is sampled and held in accordance with a sampling frequency, the input data signal thus processed is subjected to equalization and amplification, a difference in voltage (namely, height) is detected between those portions of a waveform obtained after the equalization and amplification which appear before and after a time when the waveform has a maximum voltage amplitude, a phase of that portion of the waveform which has the maximum voltage amplitude, is determined by making the above-mentioned difference equal to zero, and a clock signal synchronized with the portion having the maximum voltage amplitude is extracted and reproduced from the input data signal.
Inventors
- 👤 Keiji Tomooka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:29
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0054; H04L7/007; H03; H03K; H03K5/00; H03K5/153; H03K5/1532; H04L7/02; H04L7/033; H04L7/0331
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
301 words
A clock signal extracting circuit comprising: means for sampling and holding an input data signal in accordance with a predetermined sampling frequency to produce a train of sampled values; means for supplying a signal at said sampling frequency to said sampling and holding means to control the timing of said sampling and holding operation; means for subjecting the train of sampled values from said sampling and holding means to equalization and amplification; means connected to receive the equalized and amplified train of sampled values from said equalization and amplification means for extracting and reproducing a clock signal therefrom; means connected between said equalization and amplification means and said extracting and reproducing means for detecting a difference in voltage amplitude between a pair of those values of the equalized and amplified train of sampled values which appear immediately before and after the time when the sampled-value train has a peak value; means for controlling said sampling frequency supplied from said sampling frequency supplying means to said sampling and holding means in accordance with the output of said difference voltage detecting means so that said difference voltage is made zero, thereby providing a clock signal frequency-synchronized with said input data signal as said clock signal from said extracting and reproducing means; and means connected to receive an output of said sampling frequency supplying means varying in accordance with the output of said difference voltage detecting means for determining the phase of said input data signal at which a peak of said input data signal is to appear, said phase determining means including means for applying information of the phase of said peak to said extracting and reproducing means so that said clock signal from said extracting and reproducing means is produced as a signal phase-synchronized with the peak of said input data signal.
Claim 2
Dependent Claim
301 words
A clock signal extracting circuit comprising: means for sampling and holding an input data signal in accordance with a predetermined sampling frequency to produce a train of sampled values; means for supplying a signal at said sampling frequency to said sampling and holding means to control the timing of said sampling and holding operation; means for subjecting the train of sampled values from said sampling and holding means to equalization and amplification; means connected to receive the equalized and amplified train of sampled values from said equalization and amplification means for extracting and reproducing a clock signal therefrom; means connected between said equalization and amplification means and said extracting and reproducing means for detecting a difference in voltage amplitude between a pair of those values of the equalized and amplified train of sampled values which appear immediately before and after the time when the sampled-value train has a peak value; means for controlling said sampling frequency supplied from said sampling frequency supplying means to said sampling and holding means in accordance with the output of said difference voltage detecting means so that said difference voltage is made zero, thereby providing a clock signal frequency-synchronized with said input data signal as said clock signal from said extracting and reproducing means; and means connected to receive an output of said sampling frequency supplying means varying in accordance with the output of said difference voltage detecting means for determining the phase of said input data signal at which a peak of said input data signal is to appear, said phase determining means including means for applying information of the phase of said peak to said extracting and reproducing means so that said clock signal from said extracting and reproducing means is produced as a signal phase-synchronized with the peak of said input data signal.
Claim 3
Dependent Claim
189 words
A clock signal extracting circuit comprising: a sample and hold circuit for sampling and holding an input data signal in accordance with a predetermined sampling frequency; a equalizer for subjecting a steplike waveform to equalization and amplification, said steplike waveform being outputted from said sample and hold circuit; a rectifying circuit for rectifying the output of said equalizer; a voltage difference detecting circuit for detecting an amplitude difference voltage in a steplike waveform outputted from said rectifying circuit; a voltage controlled oscillator controlled by the output of said voltage difference detecting circuit for varying said sampling frequency; a phase-of-peak determining circuit applied with the output of said voltage controlled oscillator for determining a phase in said input data signal, a peak of said input data signal appearing at said phase, said phase-of-peak determining circuit outputting information with respect to said phase of said peak; and a discriminating circuit for discriminating a peak portion of said steplike waveform outputted from said rectifying circuit from other portions of said steplike waveform on the basis of said information with respect to said phase of said peak, to output a reproduced clock signal.
Claim 4
Dependent Claim
189 words
A clock signal extracting circuit comprising: a sample and hold circuit for sampling and holding an input data signal in accordance with a predetermined sampling frequency; a equalizer for subjecting a steplike waveform to equalization and amplification, said steplike waveform being outputted from said sample and hold circuit; a rectifying circuit for rectifying the output of said equalizer; a voltage difference detecting circuit for detecting an amplitude difference voltage in a steplike waveform outputted from said rectifying circuit; a voltage controlled oscillator controlled by the output of said voltage difference detecting circuit for varying said sampling frequency; a phase-of-peak determining circuit applied with the output of said voltage controlled oscillator for determining a phase in said input data signal, a peak of said input data signal appearing at said phase, said phase-of-peak determining circuit outputting information with respect to said phase of said peak; and a discriminating circuit for discriminating a peak portion of said steplike waveform outputted from said rectifying circuit from other portions of said steplike waveform on the basis of said information with respect to said phase of said peak, to output a reproduced clock signal.
Claim 5
Dependent Claim
18 words
A clock signal extracting circuit according to claim 2, wherein said rectifying circuit is a full-wave rectifying circuit.
Claim 6
Dependent Claim
47 words
A clock signal extracting circuit according to claim 2, wherein said voltage difference detecting circuit includes a difference detecting circuit which is made up of an MOSFET and a capacitor, and an integrating circuit which is made up of an MOSFET, a capacitor and an operational amplifier.
Claim 7
Dependent Claim
24 words
A clock signal extracting circuit according to claim 2, wherein said phase-of-peak determining circuit includes a frequency divider, a counter and an AND circuit.
Claim 8
Dependent Claim
75 words
A clock signal extracting circuit according to claim 2, wherein said discriminating circuit includes a circuit for discrminating between positive and negative values, an integrating circuit, a comparator and a flip-flop circuit, wherein said circuit for discriminating between positive and negative values is made up of an MOSFET, a capacitor and a potentiometer for setting a threshold value, and wherein said integrating circuit is made up of an MOSFET, a capacitor and an operational amplifier.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-06 | 1987-09-05 | 1988-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-06 | 1991-09-05 | 1992-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-06 | 1995-09-05 | 1996-03-06 | $7700.00 | Window Closed / Lapsed |