US4435788A
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Nonvolatile semiconductor memory device
Assignee: Texas Instruments Inc
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Filing: 1981-01-30
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Granted: 1984-03-06
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Expires: 2001-01-30
Abstract
Abstract A nonvolatile semiconductor memory device comprising a plurality of memory cells arranged in a matrix pattern and means for sensing data stored in said memory cells, characterized in that each of said memory cells comprises a pair of symmetrical submemory cells, and the pair of said submemory cells can store logic states opposite to each other.
Inventors
- 👤 Norihisa Kitagawa
- 👤 Hiroji Asahi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:40
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; G11C11/403; G11C11/404
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
105 words
A non-volatile semiconductor memory device comprising a plurality of memory cells arranged in a matrix pattern of rows and columns and row address means including separate row lines for read and write for each row and separate true and complement column lines for each column, sense amplifier means connected to the column lines for sensing data stored in said memory cells, characterized in that each of said memory cells comprises a pair of symmetrical submemory cells, each submemory cell containing a floating gate and injector means, and the pair of said submemory cells can store logic states opposite to each other on said floating gates.
Claim 2
Dependent Claim
105 words
A non-volatile semiconductor memory device comprising a plurality of memory cells arranged in a matrix pattern of rows and columns and row address means including separate row lines for read and write for each row and separate true and complement column lines for each column, sense amplifier means connected to the column lines for sensing data stored in said memory cells, characterized in that each of said memory cells comprises a pair of symmetrical submemory cells, each submemory cell containing a floating gate and injector means, and the pair of said submemory cells can store logic states opposite to each other on said floating gates.
Claim 3
Dependent Claim
42 words
A non-volatile semiconductor memory device as claimed in claim 1, characterized in that each of said sense amplifier means is a differential type sensing amplifier which compares outputs on said true and complement column lines from the pair of said submemory cells.
Claim 4
Dependent Claim
63 words
A device according to claim 2 wherein the injector means in each submemory cell is coupled to one of the column lines by a write access transistor controlled by the row line for write, and wherein the floating gate in each submemory cell is coupled to one of the column lines by a read access transistor controlled by a row line for read.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-06 | 1987-09-05 | 1988-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-06 | 1991-09-05 | 1992-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-06 | 1995-09-05 | 1996-03-06 | $7700.00 | Window Closed / Lapsed |