Unipolar voltage non-volatile JRAM cell

Claim 2

A non-volatile data storage cell having a P-channel JFET as the addressing element for the non-volatile storage element of said cell, said P-channel JFET having a source region of a higher level of impurity concentration for changing voltage breakdown threshold, wherein writing and erasing data in said cell is accomplished by voltages of the same polarity.

Claim 3

A cell as in claim 1, wherein said polarity of voltage is positive (+).

Claim 4

A cell as in claim 1, wherein said polarity of voltage is negative (-).

Claim 5

A random-access memory array of cells as in claim 1, wherein peripheral devices of said array are fabricated in NMOS technology.

Claim 6

A non-volatile data storage cell comprising: a semiconductor substrate of one conductivity type; a first region of conductivity opposite that of the substrate, extending to the surface of said substrate, wherein said first region surrounds an enclosed region of said substrate, said enclosed region of substrate having a higher level of impurity concentration of the same conductivity type as said substrate for changing the breakdown voltage between said substrate and said first region of opposite conductivity; an insulating layer covering the surface of said substrate, said first region of opposite conductivity, and said enclosed region of substrate; a multidielectric structure overlying said enclosed substrate region and recessed into said insulating layer such that a reduced thickness of said insulating layer is present between said dielectric structure and said enclosed substrate region, than is present between said substrate and subsequent structure parts; a conductor arranged on the surface of said insulating layer to be in contact with said multilayer dielectric structure.

Claim 7

A non-volatile data storage cell comprising: a semiconductor substrate of one conductivity type; a first region of conductivity opposite that of the substrate, extending to the surface of said substrate, wherein said first region surrounds an enclosed region of said substrate, said enclosed region of substrate having a higher level of impurity concentration of the same conductivity type as said substrate for changing the breakdown voltage between said substrate and said first region of opposite conductivity; an insulating layer covering the surface of said substrate, said first region of opposite conductivity, and said enclosed region of substrate; a multidielectric structure overlying said enclosed substrate region and recessed into said insulating layer such that a reduced thickness of said insulating layer is present between said dielectric structure and said enclosed substrate region, than is present between said substrate and subsequent structure parts; a conductor arranged on the surface of said insulating layer to be in contact with said multilayer dielectric structure.

Claim 8

A cell as in claim 5, wherein said semiconductor substrate is P-type.

Claim 9

A cell as in claim 5, wherein said multilayer dielectric structure comprises: a layer of silicon dioxide upon said nitride layer; a layer of titanium dioxide of a form known as rutile upon said silicon dioxide layer.

Claim 10

A cell as in claim 5, wherein said multi-layer dielectric c structure comprises: a layer of silicon nitride upon said insulating layer and overlying said enclosed region of substrate; and a layer of silicon oxide upon said layer of nitride.

Claim 11

A non-volatile data storage cell comprising: a semiconductor substrate of one conductivity type; a first region of conductivity opposite that of the substrate, wherein said first region surrounds an enclosed region of said substrate, said enclosed region of substrate having a higher level of impurity concentration of the same conductivity type as said substrate and an overlap of the multidielectric structure extending over the junction of said first region of opposite conductivity and said enclosed substrate region for changing the breakdown voltage between said substrate and said first region of opposite conductivity; an insulating layer covering the surface of said substrate, said first region of opposite conductivity, and said enclosed region of substrate; a multidielectric structure overlying said enclosed substrate region and recessed into said insulating layer such that a reduced thickness of said insulating layer is present between said dielectric structure and said enclosed substrate region, than is present between said substrate and subsequent structure parts; a conductor, arranged on the surface of said insulating layer to be in contact with said multilayer dielectric structure.

Claim 12

A non-volatile data storage cell comprising: a semiconductor substrate of one conductivity type; a first region of conductivity opposite that of the substrate, wherein said first region surrounds an enclosed region of said substrate, said enclosed region of substrate having a higher level of impurity concentration of the same conductivity type as said substrate and an overlap of the multidielectric structure extending over the junction of said first region of opposite conductivity and said enclosed substrate region for changing the breakdown voltage between said substrate and said first region of opposite conductivity; an insulating layer covering the surface of said substrate, said first region of opposite conductivity, and said enclosed region of substrate; a multidielectric structure overlying said enclosed substrate region and recessed into said insulating layer such that a reduced thickness of said insulating layer is present between said dielectric structure and said enclosed substrate region, than is present between said substrate and subsequent structure parts; a conductor, arranged on the surface of said insulating layer to be in contact with said multilayer dielectric structure.