Method for conditional branch execution in SIMD vector processors

Claim 1

A two-phase method for controlling the execution of a program consisting of a single entrance, single exit (SESE) program instruction sequences on a single instruction, multiple datastream (SIMD) machine during a second phase, which SESE instruction sequences were previously conditioned from an ordinary program instruction sequence on a single instruction, single datastream (SISD) machine during a first phase, said SIMD machine includes an array of parallel processors; means for applying independent datastreams to counterpart processors, each processor having an activity mask (active, inactive); and a control unit for applying the program to the processors to interact with the data and for regulating the activity state of each processor by altering its activity mask contents, wherein: during the first phase, the steps of: (a) compiling an ordinary program and decomposing it into SESE instruction sequences, the last instruction in each sequence being either an unconditional or conditional branch; (b) priority ordering the sequences according to a depth ordering convention and assigning sequence label numbers thereto linearly; and (c) inserting either a ELSE or JOIN instruction at the beginning of sequences selected according to a first predetermined convention; and during the second phase, the steps of: (d) causing a SESE sequence processed during the first phase to be executed on one or more processors of an SIMD machine in parallel; and causing the designation of the next executable SESE sequence as a function of the matching or mismatching of the SESE sequence targets of the branches of the sequence currently being executed on one or more processors according to a second predetermined convention; (e) upon occurrence of a branch instruction, ascertaining the targets and, if there does not exist a target to a successful conditional branch, transferring control to the unique target, otherwise transferring control to the target of the successful conditional branch and masking off as inactive the processors corresponding to the target of the unsuccessful conditional branch; (f) upon the occurrence of an ELSE instruction in said current SESE sequence as applied to the SIMD machine, ascertaining the next SESE target sequence having the lowest priority order number; masking on into an active state each inactive processor awaiting execution of the ascertained target SESE sequence; and masking off into an inactive state all other processors waiting to execute other SESE sequences; or (g) upon the occurrence of a JOIN instruction in said current SESE sequence as applied to the SIMD machine, masking on into an active state those inactive processors waiting to execute SESE sequences having a priority order number the same as that of the SESE sequence currently being executed by the SIMD machine.