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US4435655A
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Log-conformance error correction circuit for semiconductor devices
Assignee: Maxim Integrated Products Inc
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Filing: 1981-05-18
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Granted: 1984-03-06
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Expires: 2001-05-18
Abstract
Abstract A log-conformance correction circuit for a prototype circuit employing semiconductor devices comprises a quad of devices with voltage drops arranged in series, and currents or current densities driven such that the logarithmic components in the voltage drops sum to zero while log-conformance error components are produced. A correction quad suitably may comprise two pairs of semiconductor devices in which the current densities in one pair are cross-proportional with the current densities of the other pair, and of a different magnitude to establish a current density ratio between the pairs. The log-conformance error components which are generated by the correction quad are inserted into the prototype circuit to cancel log-conformance error therefrom.
Inventors
- 👤 Max W. Hauser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:43
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/24
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
91 words
A circuit for correcting log-conformance error in a prototype circuit which includes semiconductor junctions, comprising: a first pair of semiconductor devices; and a second pair of semiconductor devices operatively associated with said first pair of semiconductor devices such that the current densities of said second pair are cross-proportional with the current densities of said first pair and of a different magnitude; wherein signal-dependent current derived from said prototype circuit flows through said first and second pairs of semiconductor devices and a correction voltage is generated thereby for correcting said log-conformance error.
Claim 2
Dependent Claim
91 words
A circuit for correcting log-conformance error in a prototype circuit which includes semiconductor junctions, comprising: a first pair of semiconductor devices; and a second pair of semiconductor devices operatively associated with said first pair of semiconductor devices such that the current densities of said second pair are cross-proportional with the current densities of said first pair and of a different magnitude; wherein signal-dependent current derived from said prototype circuit flows through said first and second pairs of semiconductor devices and a correction voltage is generated thereby for correcting said log-conformance error.
Claim 3
Dependent Claim
38 words
A circuit in accordance with claim 1 wherein said first and second pairs of semiconductor devices include semiconductor junctions wherein the respective junctions of said first pair are connected in series with respective junctions of said second pair.
Claim 4
Dependent Claim
107 words
A correction quad for correcting log-conformance error in a circuit employing semiconductor devices, comprising: an upper pair of semiconductor junction devices through which signal-dependent current of said circuit flows; and a lower pair of semiconductor junction devices through which said signal-dependent current flows, respective ones of the lower pair of semiconductor junction devices being connected in series with respective ones of said upper pair of semiconductor junction devices, wherein the current densities of said lower pair are process-proportional with the current densities of said upper pair, and the magnitude of current densities of said lower pair differs from that of said upper pair by a predetermined ratio.
Claim 5
Dependent Claim
107 words
A correction quad for correcting log-conformance error in a circuit employing semiconductor devices, comprising: an upper pair of semiconductor junction devices through which signal-dependent current of said circuit flows; and a lower pair of semiconductor junction devices through which said signal-dependent current flows, respective ones of the lower pair of semiconductor junction devices being connected in series with respective ones of said upper pair of semiconductor junction devices, wherein the current densities of said lower pair are process-proportional with the current densities of said upper pair, and the magnitude of current densities of said lower pair differs from that of said upper pair by a predetermined ratio.
Claim 6
Dependent Claim
55 words
A correction quad in accordance with claim 3 wherein said semiconductor junction devices comprise transistors arranged in a loop such that logarithmic components in the base-to-emitter voltage drops sum to zero while a log-conformance error component is developed which is equal in amplitude and of opposite polarity to the log-conformance error produced by said circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-06 | 1987-09-05 | 1988-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-06 | 1991-09-05 | 1992-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-06 | 1995-09-05 | 1996-03-06 | $7700.00 | Window Closed / Lapsed |