System of numerical transmission with adaptative coding, of analogical information sampled and transformed by orthogonal transformation

Claim 3

A digital transmission system with an adaptative coding of sampled analogic information, the coding being digitized samples which are binary bits which have been subjected to an orthogonal transformation, with an adaptative threshold type of reduction of data flow rate, said system comprising coding means having an orthogonal transformation transformer means to which the digitized binary bits are applied, threshold evaluating means for detecting a predetermined data flow rate, multiplexer means, coding circuit means responsive to said transformer and to said threshold evaluating means for delivering a coded output of data to an input of said multiplexer means, said coding circuit means further comprising a combining logic decoding means having one input coupled to the output of said transformer means, another input of said logic decoding means being coupled to the output of said threshold evaluation means, and a third input of said logic decoding means being driven by a clock signal which recurs at a frequency which is twice the frequency of the binary bits delivered by said transformer, and a fourth input coupled to an end of data output of the coding circuit means, and an output of said coding means being connected to a data input of said multiplexer means, said logic decoding means producing a complementary coding.

Claim 4

A digital transmission system with an adaptative coding of sampled analogic information, the coding being digitized samples which are binary bits which have been subjected to an orthogonal transformation, with an adaptative threshold type of reduction of data flow rate, said system comprising coding means having an orthogonal transformation transformer means to which the digitized binary bits are applied, threshold evaluating means for detecting a predetermined data flow rate, multiplexer means, coding circuit means responsive to said transformer and to said threshold evaluating means for delivering a coded output of data to an input of said multiplexer means, said coding circuit means further comprising a combining logic decoding means having one input coupled to the output of said transformer means, another input of said logic decoding means being coupled to the output of said threshold evaluation means, and a third input of said logic decoding means being driven by a clock signal which recurs at a frequency which is twice the frequency of the binary bits delivered by said transformer, and a fourth input coupled to an end of data output of the coding circuit means, and an output of said coding means being connected to a data input of said multiplexer means, said logic decoding means producing a complementary coding.

Claim 5

A system according to claim 2, characterized in that said logic decoding means comprises a field programmable logic array means, and first in first out memory means, the field programmable logic array means having two outputs respectively connected to recording and data inputs of the first in first out memory means, reading input means coupled to said memory means for responding to an end of data signal out of the coding circuit means, and data output means on said memory means connected to the input of said multiplexer means.

Claim 6

A transmission system according to claim 2 or 3, and a decoding means comprising a logical decoding means which receives the transmitted signals, said logical decoding means having an output which delivers basic data relating to coefficients, a second output which delivers complementary data, a fourth output which delivers a signal for validation of the data, and inverted transformer means for decoding the orthogonal transformation with respect to the output of the coding means, the first output of said logical decoding means being connected to a first input of an OR circuit, and to a first input of a logic operator means, said logic operator means responding to the complementary codes, a second threshold output of said logic decoding means being coupled to an input of said logic operator means and a logic fourth output of said logic decoding means being connected to receive said fourth output signal having a frequency which is twice the binary bit rate, the output of said logic operator means being coupled to a second input of the OR circuit, and the output of the OR circuit being coupled to the inverted transformer means for delivering the codes of the signal.