Off-chip access for psuedo-microprogramming in microprocessor

Claim 2

A microprocessor comprising: a main memory containing a plurality of locations defined by an address space, the main memory having an address input, a data output and a control input, a central processing unit in a semiconductor unit separate from said main memory, said central processing unit including an arithmetic logic unit, a plurality of registers, a program counter, an instruction register for receiving program instructions addressed by said program counter for execution by the central processing unit, such program instructions being of a predetermined instruction set as stored in said main memory, and control means responsive to the program instructions of said instruction set in said instruction register to produce a plurality of controls for defining the operation of the central processing unit and for generating memory controls, bus means connecting terminals of the central processing unit to the address input and data output of said main memory to transfer addresses from the program counter of the central processing unit to said main memory and to transfer instructions from said main memory to the central processing unit, the number of bits of said program counter and said bus means for such addresses defining the size of said address space, said bus means also transferring said memory controls from said control means to said control input of said main memory, a first storage means containing sequences of program instructions in a plurality of memory locations defined by a first set of addresses, and means coupling addresses from said program counter to the first storage means to fetch instructions while disabling said main memory by said memory controls whereby the first set may overlap said address space, a separate second storage means containing sequences of program instructions in a plurality of memory locations defined by a second set of addresses, and means coupling addresses from said program counter to the second storage means to fetch instructions while disabling said main memory by said memory controls whereby the second set may overlap said address space, and means initiated by the control means in response to predetermined program instructions, for transferring sequences of program instructions from such first or second storage means to said instruction register, such sequences being instructions of said instruction set.

Claim 3

Apparatus according to claim 1 wherein said first storage means is on a single semiconductor integrated circuit with said central processing unit.

Claim 4

Apparatus according to claim 2 wherein said main memory is not on said integrated circuit.

Claim 5

Apparatus according to claim 3 wherein said second storage means is not on said integrated circuit.

Claim 6

Apparatus according to claim 4 wherein said first and second storage means are activated in the alternative.

Claim 7

A microprocessor system comprising: (a) a first memory containing a plurality of locations with a first set of addresses defining a first memory map, the first memory containing program instructions and data, (b) input/output means for receiving and transmitting information, (c) a central processing unit connected to said first memory and said input/output means by conductor means to couple addresses, program instructions, data and information between the memory, input/output means and central processing means, said central processing unit being constructed in a single semiconductor device and comprising: an arithmetic logic unit for performing arithmetic and logic operations on data, a plurality of registers for containing addresses and data, a program counter coupled to said conductor means, an instruction register for receiving program instructions addressed by the program counter for execution by the central processing unit, such program instructions being of a predetermined instruction set, the number of bits in the program counter defining the size of said first memory map, control means responsive to the program instruction in said instruction register to produce a plurality of controls for defining the operation of the central processing unit, and for generating memory controls, a second memory within said device containing sequences of program instructions in a plurality of locations with a second set of addresses defining a second memory map, wherein the second set of addresses may overlap said given first set of addresses, said second memory including a control input receiving said memory controls from said control means, with addressing means initiated by the memory controls from said control means in response to predetermined program instructions for transferring said sequences of program instructions from such second memory to said instruction register as addressed by the program counter in response to predetermined program instructions, such sequences being composed of instructions of said instruction set, and (d) a third memory separate from said device connected to the device by said conductor means and containing sequences of program instructions in a plurality of locations with a third set of addresses not within said second memory map, said third memory means including a control input receiving said memory controls from said control means, said addressing means transferring said sequences of program instructions from said third memory to said instruction register via said conductor means for addresses within the third set.

Claim 8

A microprocessor system comprising: (a) a first memory containing a plurality of locations with a first set of addresses defining a first memory map, the first memory containing program instructions and data, (b) input/output means for receiving and transmitting information, (c) a central processing unit connected to said first memory and said input/output means by conductor means to couple addresses, program instructions, data and information between the memory, input/output means and central processing means, said central processing unit being constructed in a single semiconductor device and comprising: an arithmetic logic unit for performing arithmetic and logic operations on data, a plurality of registers for containing addresses and data, a program counter coupled to said conductor means, an instruction register for receiving program instructions addressed by the program counter for execution by the central processing unit, such program instructions being of a predetermined instruction set, the number of bits in the program counter defining the size of said first memory map, control means responsive to the program instruction in said instruction register to produce a plurality of controls for defining the operation of the central processing unit, and for generating memory controls, a second memory within said device containing sequences of program instructions in a plurality of locations with a second set of addresses defining a second memory map, wherein the second set of addresses may overlap said given first set of addresses, said second memory including a control input receiving said memory controls from said control means, with addressing means initiated by the memory controls from said control means in response to predetermined program instructions for transferring said sequences of program instructions from such second memory to said instruction register as addressed by the program counter in response to predetermined program instructions, such sequences being composed of instructions of said instruction set, and (d) a third memory separate from said device connected to the device by said conductor means and containing sequences of program instructions in a plurality of locations with a third set of addresses not within said second memory map, said third memory means including a control input receiving said memory controls from said control means, said addressing means transferring said sequences of program instructions from said third memory to said instruction register via said conductor means for addresses within the third set.

Claim 9

A system according to claim 6 wherein said second memory is on a single semiconductor integrated circuit with said central processing unit.

Claim 10

A system according to claim 7 wherein said first memory and said third memory are not on said integrated circuit.

Claim 11

Apparatus according to claim 8 wherein said second memory and said third memory are accessed in the alternative.

Claim 12

Apparatus according to claim 8 wherein said second memory is deactivated when accessing the third memory.

Claim 13

Apparatus according to claim 8 wherein said first memory map is limited by the logical address space allowed by the number of bits of addresses coupled by said conductor means.