First-in first-out storage and processing unit making use thereof

Claim 2

A first-in first-out memory comprising: a plurality of memory banks each capable of read and write modes of operation; first indicating means for generating a mode indicating signal sequentially and cyclically indicating a write mode of operation for said memory banks in a predetermined order in response to a clock signal; write control means responsive to said mode indicating signal and sequentially received data signals for writing said sequentially received data signals into different ones of said memory banks according to said predetermined order and at the sequential timings when said write mode is indicated for said different memory banks; second indicating means responsive to an applied read request signal for generating a read address signal indicating an address of one of said memory banks for effecting readout of the next data signal; and read control means responsive to said mode indicating signal and said read address signal for reading out said next data signal from said indicated address of said one memory bank, including first means for detecting the presence of said next data signal in a memory bank in dependence on the difference between the total number of data signals already written into the memory banks and the number of data signals already read out of said memory banks and second means for reading out said next data signal when said one memory bank is not in a write mode.

Claim 3

A first-in first-out memory according to claim 1, wherein said read control means further includes third means for generating a read OK signal which indicates that the next data signal is present in a memory bank, at a timing when said write mode is not indicated to said one memory bank and the result of said detection by said first means is positive.

Claim 4

A first-in first-out memory according to claim 2, wherein said read control means further includes fourth means responsive to said read address signal and said mode indicating signal for reading data from one of said memory banks which is not enabled to operate in said write mode, said one memory bank being changed between write and read modes of operation sequentially and cyclically in response to said clock signal.

Claim 5

A first-in first-out memory according to claim 2, wherein said plurality of memory banks comprise first and second memory banks; said first indicating means comprises means for alternately enabling said first and second memory banks to operate in the write mode in response to said clock signal; and said read control means further includes means for alternately indicating one of said first and second memory banks in response to receipt of said read request signal.

Claim 6

A first-in first-out memory according to claim 4, wherein said write control means includes a binary write address counter, means for changing the value of said write address counter when either of said first and second memory banks receives a data signal, and means for applying the output of said write address counter except for the lowest order bit thereof as a write address for the next writing operation for either memory bank.

Claim 7

A first-in first-out memory according to claim 4, wherein said read control means includes means for alternately reading data from one of said first and second memory banks in response to said mode indicating signal when said one bank is not enabled to operate in said write mode.

Claim 8

A first-in first-out memory according to claim 6, wherein said means for alternately reading data comprises means for selectively transferring output data from said first and second memory banks in response to said mode indicating signal.

Claim 9

A first-in first-out memory according to claim 6, wherein said first means includes means for effecting said detection in response to said clock signal, and said generating means includes means for detecting coincidence in response to said clock signal between said one memory bank and said indicated memory bank in the write mode.

Claim 10

A first-in first-out memory comprising even and odd memory banks for storing even and odd ones of a plurality of sequentially received data items, respectively, in response to an applied write enable signal and a memory address and for reading out stored data items in response to an applied memory address in the absence of a write enable signal; mode indicating means for alternately generating first and second write indicating signals designating the write mode periods for said even and odd memory banks, respectively; write control means connected to receive a write request signal and a data item for generating a write enable signal only when the received data item is to be stored in one of said memory banks which is in its write mode period as indicated by said write indicating signals; write enabling means connected to said mode indicating means and said write control means for applying said write enable signal, said data item and a memory address to the one of said even and odd memory banks which is in its write mode period as indicated by said write indicating signals; read control means responsive to a received read request signal for generating sequential read address signals when data items are stored in at least one of said memory banks; read enabling means connected to said mode indicating means and said read control means for applying said read address signal to said even and odd memory banks alternately in response to said write indicating signals so that said read address signals are applied to said memory banks during times when they are not in their write mode periods; and output means for transmitting data items read from said even and odd memory banks to an output terminal.

Claim 11

A first-in first-out memory comprising even and odd memory banks for storing even and odd ones of a plurality of sequentially received data items, respectively, in response to an applied write enable signal and a memory address and for reading out stored data items in response to an applied memory address in the absence of a write enable signal; mode indicating means for alternately generating first and second write indicating signals designating the write mode periods for said even and odd memory banks, respectively; write control means connected to receive a write request signal and a data item for generating a write enable signal only when the received data item is to be stored in one of said memory banks which is in its write mode period as indicated by said write indicating signals; write enabling means connected to said mode indicating means and said write control means for applying said write enable signal, said data item and a memory address to the one of said even and odd memory banks which is in its write mode period as indicated by said write indicating signals; read control means responsive to a received read request signal for generating sequential read address signals when data items are stored in at least one of said memory banks; read enabling means connected to said mode indicating means and said read control means for applying said read address signal to said even and odd memory banks alternately in response to said write indicating signals so that said read address signals are applied to said memory banks during times when they are not in their write mode periods; and output means for transmitting data items read from said even and odd memory banks to an output terminal.

Claim 12

A first-in first-out memory according to claim 9, wherein said write control means includes means for detecting from said received write request signal whether the received data item is to be stored in said even or odd memory bank.

Claim 13

A first-in first-out memory according to claim 10, wherein said write control means includes means for temporarily storing the received data item when said data item is received at a time when the memory bank into which it is to be stored is not in its write mode period.

Claim 14

A first-in first-out memory according to claim 10, wherein said write control means includes means for storing a memory address signal to be applied to said write enabling means along with said write enable signal and means responsive to receipt of said write request signal for incrementing said memory address signal in said storing means.

Claim 15

A first-in first-out memory according to claim 9, wherein said read control means includes means for storing a read address signal to be applied to said read enabling means and means responsive to said read request signal for incrementing said read address signal in said storing means.

Claim 16

A first-in first-out memory according to claim 9, wherein said read control means includes means responsive to said write request signal and said read request signal for determining whether a data item remains in at least one of said memory banks to be read out.

Claim 17

A first-in first-out memory according to claim 9, including more than two memory banks, and wherein said mode indicating means operates to generate sequentially a write indicating signal for each of said memory banks.