Patent US4433389A successfully refreshed from Google Patents.
US4433389A
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Memory address translation system for accessing memory locations via job names
Assignee: Unisys Corp
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Filing: 1981-03-16
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Granted: 1984-02-21
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Expires: 2001-03-16
Abstract
Abstract In a named data processing system having a plurality of memory modules, each module therein having a plurality of locations for storing data pages and the like, a memory address translation apparatus and method translates a data job name and associated segmented address field into a memory module-page addressing pair wherein each and every storage location may be accessed by each and every job name. The job name and the associated segmented address field are each partitioned into most and least significant bit fields. Through translation a storage location is defined by the exclusive ORing of the least significant fields of the data job name and segmented address field. Likewise a memory module is defined by the exclusive ORing of the most significant fields of the job name and the segmented address field as permuted by an exclusive ORing with the least significant field of the segmented address field. Preferably, in order to increase address spacing activity, the most significant field of the job name is processed through a Fibonacci hashing process before any exclusive ORing process.
Inventors
- 👤 Kenneth L. York
- 👤 Oscar B. Stram
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:13
CPC Classifications
G; G06; G06F; G06F16/00; G06F16/90; G06F16/901; G06F16/9014; G06F12/00; G06F12/02; G06F12/08; G06F12/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
317 words
A memory address translation apparatus for a data storage system having a plurality of memory modules, each memory module therein having a plurality of addressable storage locations, said data storage system addressed by a data name and an address segment, each data name and each address segment having a plurality of least significant bits and a plurality of most significant bits, said memory address translation apparatus comprising: storage location address means including least significant bit means receiving said plurality of least significant bits of said data name and said address segment for exclusively ORing said received plurality of least significant bits of said data name with said received plurality of least significant bits of said address segment to generate at the output thereof the address of an addressable storage location in said plurality thereof; and memory module address means including most significant bit means, permuting means and adder means; said most significant bit means receiving said plurality of most significant bits of said data name and said address segment for exclusively ORing said received plurality of most significant bits of said data name with said received plurality of most significant bits of said address segment and for generating an output thereof; said permuting means receiving said output of said most significant bit means and said plurality of said least significant bits of said address segment for exclusively ORing the output of said most significant bit means with said plurality of least significant bits of said address segment and for generating an output thereof; and said adder means receiving said output of said permuting means and said output of said least significant bit means for adding in modulo N fashion said output of said permuting means with said output of said least significant bit means to address a memory module in said plurality thereof, said N being equal to the number of memory modules in said plurality thereof.
Claim 2
Dependent Claim
317 words
A memory address translation apparatus for a data storage system having a plurality of memory modules, each memory module therein having a plurality of addressable storage locations, said data storage system addressed by a data name and an address segment, each data name and each address segment having a plurality of least significant bits and a plurality of most significant bits, said memory address translation apparatus comprising: storage location address means including least significant bit means receiving said plurality of least significant bits of said data name and said address segment for exclusively ORing said received plurality of least significant bits of said data name with said received plurality of least significant bits of said address segment to generate at the output thereof the address of an addressable storage location in said plurality thereof; and memory module address means including most significant bit means, permuting means and adder means; said most significant bit means receiving said plurality of most significant bits of said data name and said address segment for exclusively ORing said received plurality of most significant bits of said data name with said received plurality of most significant bits of said address segment and for generating an output thereof; said permuting means receiving said output of said most significant bit means and said plurality of said least significant bits of said address segment for exclusively ORing the output of said most significant bit means with said plurality of least significant bits of said address segment and for generating an output thereof; and said adder means receiving said output of said permuting means and said output of said least significant bit means for adding in modulo N fashion said output of said permuting means with said output of said least significant bit means to address a memory module in said plurality thereof, said N being equal to the number of memory modules in said plurality thereof.
Claim 3
Dependent Claim
22 words
The memory address translation apparatus of claim 1 wherein said means for combining in modulo N fashion includes a modulo N adder.
Claim 4
Dependent Claim
47 words
The memory address translation apparatus of claim 1 wherein said means for combining in modulo N fashion includes a two dimensional matrix addressed in one dimension by the output of said permuting means and in the other dimension by the output of said least significant bit means.
Claim 5
Dependent Claim
33 words
The memory address translation apparatus of claim 1 further including: means for scrambling said plurality of most significant bits of said data name prior to providing same to said most significant bit means.
Claim 6
Dependent Claim
27 words
The memory address translation apparatus of claim 4 wherein said means for scrambling applies Fibonacci hashing to said plurality of most significant bits of said data name.
Claim 7
Dependent Claim
22 words
The memory address translation apparatus of claim 5 wherein said means for combining in modulo N fashion includes a modulo N adder.
Claim 8
Dependent Claim
46 words
The memory address translation apparatus of claim 6 wherein said means for combining in modulo N fashion includes a two dimensional matrix addressed in one dimension by the output of said permuting means and in the other dimension by output of said least significant bit means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-20 | 1987-08-22 | 1988-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-20 | 1991-08-22 | 1992-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-20 | 1995-08-22 | 1996-02-21 | $7700.00 | Window Closed / Lapsed |