Patent US2373642A successfully refreshed from Google Patents.
Patent US4433305A successfully refreshed from Google Patents.
US4433305A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Amplifier circuit
Assignee: Pioneer Corp
•
Filing: 1980-09-19
•
Granted: 1984-02-21
•
Expires: 2000-09-19
Abstract
Abstract A push-pull amplifier circuit using bipolar transistors in which non-linear distortion caused by the base-emitter voltages of the amplifying transistors of the circuit is eliminated without the use of negative AC feedback and in which variations in a DC output level at the output terminal of the amplifier are detected and fed back to the input side of the amplifier whereby the stability of the circuit at very low frequencies is remarkably improved. A first amplifier stage includes a first transistor having a base to which an input signal is applied and a second transistor the base of which is coupled to an output of the first transistor with the second transistor being of the opposite conductivity type to the first transistor. A current mirror circuit supplies currents to the first and second transistors with the currents thus supplied having a constant ratio. A second amplifying stage is provided having the same construction. A load is coupled to be driven by the current flowing through the first transistor in the first amplifying stage and by the corresponding transistor in the second amplifying stage. Variations in the output of the circuit are detected to provide a DC feedback voltage which is coupled back to emitter circuits in the input stages of the amplifier.
Inventors
- 👤 Akio Ozawa
- 👤 Susumu Sueyoshi
- 👤 Keishi Sato
- 👤 Kikuo Ishikawa
- 👤 Kiyomi Yatsuhashi
- 👤 Satoshi Ishii
- 👤 Masamichi Yumino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:47
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/26; H03F1/00; H03F1/32; H03F1/3217; H03F1/34; H03F3/30; H03F3/3069; H03F3/3076
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
105 words
An amplifier circuit comprising: a first transistor having a base to which an input signal is applied; a second transistor of the conductivity type opposite that of said first transistor having a base coupled to an emitter of said first transistor; means for supplying currents to said emitter of said first transistor and a collector of said second transistor, the ratio of said currents being constant; and at least one resistor coupled in series with at least one of said collector and an emitter of said second transistor for producing an output signal having a component in proportion to said current in said second transistor.
Claim 2
Dependent Claim
105 words
An amplifier circuit comprising: a first transistor having a base to which an input signal is applied; a second transistor of the conductivity type opposite that of said first transistor having a base coupled to an emitter of said first transistor; means for supplying currents to said emitter of said first transistor and a collector of said second transistor, the ratio of said currents being constant; and at least one resistor coupled in series with at least one of said collector and an emitter of said second transistor for producing an output signal having a component in proportion to said current in said second transistor.
Claim 3
Dependent Claim
17 words
The amplifier as defined in claim 1 wherein said current supplying means comprises a current mirror circuit.
Claim 4
Dependent Claim
30 words
The amplifier as defined in claim 1 or 2 further comprising means for feeding back a signal representing variations in an output of said amplifier to a predetermined circuit point.
Claim 5
Dependent Claim
114 words
An amplifier circuit comprising: a first transistor having a base to which an input signal is applied; a second transistor having a base to which an emitter of said first transistor is coupled, said second transistor being opposite in conductivity type to said first transistor; means for supplying currents to said emitter of said first transistor and a collector of said second transistor, said currents having a constant ratio; means for providing an output having a component in proportion to the current flowing through said second transistor; and means for detecting variations in the output of said output providing means to provide a feedback voltage corresponding to said variations to a predetermined circuit point.
Claim 6
Dependent Claim
114 words
An amplifier circuit comprising: a first transistor having a base to which an input signal is applied; a second transistor having a base to which an emitter of said first transistor is coupled, said second transistor being opposite in conductivity type to said first transistor; means for supplying currents to said emitter of said first transistor and a collector of said second transistor, said currents having a constant ratio; means for providing an output having a component in proportion to the current flowing through said second transistor; and means for detecting variations in the output of said output providing means to provide a feedback voltage corresponding to said variations to a predetermined circuit point.
Claim 7
Dependent Claim
26 words
The amplifier circuit as defined in claim 4 wherein the output of said detecting means is fed back to the emitter side of said second transistor.
Claim 8
Dependent Claim
36 words
The amplifier circuit as defined in claim 4 wherein said first transistor is connected in an emitter follower configuration, the emitter follower output of said first transistor being applied to the base of said second transistor.
Claim 9
Dependent Claim
244 words
An amplifier circuit comprising: a first PNP transistor, the base of said first PNP transistor being coupled to an input terminal; a second NPN transistor, the base of said second NPN transistor being coupled to the emitter of said first PNP transistor; a third PNP transistor, the collector of said third PNP transistor being coupled to said emitter of said first PNP transistor; a fourth PNP transistor, the base of said fourth PNP transistor being coupled to the base of said third PNP transistor and to the collector of said fourth PNP transistor and to the collector of said second NPN transistor; a first positive voltage source and first and second negative voltage sources, the collector of said first PNP transistor being coupled to said first negative voltage source; first and second resistors coupled in series with each other between the emitter of said second NPN transistor and said second negative voltage source; a third resistor coupled between the emitter of said fourth PNP transistor and said positive voltage source, said emitter of said fourth PNP transistor being coupled to an output terminal; a fourth resistor coupled between the emitter of said third PNP transistor and said positive voltage source; means for producing a signal representing variations in the DC level of the signal upon said output terminal; and means for inverting the polarity of said signal representing said variations, the inverter signal being coupled to the junction between said first and second resistors.
Claim 10
Dependent Claim
244 words
An amplifier circuit comprising: a first PNP transistor, the base of said first PNP transistor being coupled to an input terminal; a second NPN transistor, the base of said second NPN transistor being coupled to the emitter of said first PNP transistor; a third PNP transistor, the collector of said third PNP transistor being coupled to said emitter of said first PNP transistor; a fourth PNP transistor, the base of said fourth PNP transistor being coupled to the base of said third PNP transistor and to the collector of said fourth PNP transistor and to the collector of said second NPN transistor; a first positive voltage source and first and second negative voltage sources, the collector of said first PNP transistor being coupled to said first negative voltage source; first and second resistors coupled in series with each other between the emitter of said second NPN transistor and said second negative voltage source; a third resistor coupled between the emitter of said fourth PNP transistor and said positive voltage source, said emitter of said fourth PNP transistor being coupled to an output terminal; a fourth resistor coupled between the emitter of said third PNP transistor and said positive voltage source; means for producing a signal representing variations in the DC level of the signal upon said output terminal; and means for inverting the polarity of said signal representing said variations, the inverter signal being coupled to the junction between said first and second resistors.
References Cited (Backward Citations)
US4103248A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-20 | 1987-08-22 | 1988-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-20 | 1991-08-22 | 1992-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-20 | 1995-08-22 | 1996-02-21 | $7700.00 | Window Closed / Lapsed |