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US4431930A Expired / Lapsed US ⏱️ 0.0 years remaining

Digital time domain noise filter

Assignee: National Semiconductor Corp
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Filing: 1981-10-05
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Granted: 1984-02-14
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Expires: 2001-10-05
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Abstract

Abstract A trigger circuit with hysteresis is created by driving a latch circuit set and reset terminals through a pair of emitter driven complementary transistors the bases of which are returned to a reference potential V REF . The hysteresis is set by the V BE potentials of the complementary transistors. When the input emitters are driven more than one V BE above V REF , one transistor will conduct and set the latch. When the input falls below one V BE below V REF , the other transistor will conduct and reset the latch. A digital filter is created by coupling a capacitor across the trigger circuit input and digitally driving the capacitor through a transconductance amplifier.

Inventors

  • 👤 Dennis M. Monticelli

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 22:45
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252; H04; H04L; H04L1/00; H04L1/20

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 120 words
A trigger circuit comprising: latch means having a digital output and set and reset input means; a pair of complementary input transistors having their outputs respectively coupled to said set and reset inputs wherein one of said complementary transistor outputs is directly coupled to said latch and the other transistor output is coupled by way of a current mirror; means for coupling the control electrodes of said complementary transistors in common to a source of reference potential; and means for coupling the input electrodes of said complementary transistors in common to a signal input circuit whereby said latch changes state when said signal input rises to a first threshold level and when said input falls below a second threshold level.
Claim 2
Dependent Claim 120 words
A trigger circuit comprising: latch means having a digital output and set and reset input means; a pair of complementary input transistors having their outputs respectively coupled to said set and reset inputs wherein one of said complementary transistor outputs is directly coupled to said latch and the other transistor output is coupled by way of a current mirror; means for coupling the control electrodes of said complementary transistors in common to a source of reference potential; and means for coupling the input electrodes of said complementary transistors in common to a signal input circuit whereby said latch changes state when said signal input rises to a first threshold level and when said input falls below a second threshold level.
Claim 3
Dependent Claim 24 words
The trigger circuit of claim 1 wherein said current mirror comprises a dual collector PNP transistor having one collector directly coupled to its base.
Claim 4
Dependent Claim 24 words
The trigger circuit of claim 1 in further combination with a digital signal source and a ramp generator to create a digital noise filter.
Claim 5
Dependent Claim 65 words
The filter of claim 3 wherein said ramp generator comprises a transconductance amplifier coupled to said digital signal source and a capacitor coupled to its output whereby said capacitor charges and discharges in response to said transconductance amplifier output current thereby generating a ramp function in response to the digital input and whereby digital noise signals narrower than the duration of said ramp are removed.

References Cited (Backward Citations)

US3054910A Cited
US3018386A Cited
US3230521A Cited
US3192403A Cited
US3260943A Cited
US3460000A Cited
US3737682A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-02-13 1987-08-15 1988-02-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-02-13 1991-08-15 1992-02-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-02-13 1995-08-15 1996-02-14 $7700.00 Window Closed / Lapsed

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