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US4430792A
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US
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Minimal mask process for manufacturing insulated-gate semiconductor devices with integral shorts
Assignee: Fairchild Semiconductor Corp
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Filing: 1982-08-09
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Granted: 1984-02-14
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Expires: 2002-08-09
Abstract
Abstract Processes for manufacturing insulated-gate semiconductor devices such as MOSFETs wherein the source and base regions and the source-to-base ohmic short are formed employing self-aligned masking techniques are disclosed. In the exemplary case of a MOSFET, the processes begin with a semiconductor wafer (such as silicon) including a drain region, a gate insulating layer initially formed uniformly on the surface of the drain region, and a polysilicon conductive gate layer. Through subsequent masking and etching steps, channels are etched through the polysilicon gate layer at least to the drain region. The un-etched portions define polysilicon gate electrodes spaced along the drain region. A two-stage polysilicon etch procedure is disclosed. An initial etch step produces relatively narrow channels. Unetched portions of the polysilicon layer are then used as masks to form a shorting extension of the device base region, preferably by ion implantation. In a subsequent lateral etch step, previously un-etched portions of the polysilicon gate electrode layer are etched to define insulated polysilicon gate electrode structures extending upwardly from and spaced along the principal surface. MOSFET source and base regions are then formed, preferably by vertical ion implantation, employing the polysilicon gate electrode structures as masks. Appropriate electrode metallization is applied.
Inventors
- 👤 Victor A. K. Temple
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:32
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10D18/00; H10D18/40; H10D64/00; H10D64/01; H10D64/011
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
316 words
A self-aligned process for manufacturing an insulated-gate semiconductor device including an integral short, said process comprising: providing a semiconductor wafer including a first region of one conductivity type having a principal surface, and preparing the wafer by forming on the principal surface a gate insulating region layer, and forming on the gate insulating region layer a conductive gate electrode layer; forming an etch resist mask having openings defining the ultimate locations of upper electrode regions, and initially etching in areas defined by the mask openings through the gate electrode layer at least to the gate insulating layer with minimal undercutting of the etch resist mask; introducing into the first region impurities appropriate to form a shorting region of the opposite conductivity type while employing un-etched portions of the gate electrode layer as a mask; laterally etching the previously un-etched portions of the gate electrode layer, thereby defining gate electrodes extending upwardly from and spaced along the gate insulating layer and first region principal surface; introducing into the first region between the gate electrodes impurities appropriate to form a base region of opposite conductivity type and an upper electrode region of the one conductivity type within the base region, the gate electrodes serving as masks during the introduction of impurities, and diffusing the impurities introduced to appropriately locate and configure the base and upper electrode regions such that at the principal surface the base region exists as a band of opposite conductivity type between the upper electrode region and the first region, with active portions of the band underlying at least a portion of at least one gate electrode and being separated by portions of the gate insulating layer; oxidizing at least the gate electrode sidewalls; and forming a metallized upper electrode region terminal in ohmic contact with the upper electrode and shorting regions, and forming a metallized gate terminal in ohmic contact with the gate electrode.
Claim 2
Dependent Claim
316 words
A self-aligned process for manufacturing an insulated-gate semiconductor device including an integral short, said process comprising: providing a semiconductor wafer including a first region of one conductivity type having a principal surface, and preparing the wafer by forming on the principal surface a gate insulating region layer, and forming on the gate insulating region layer a conductive gate electrode layer; forming an etch resist mask having openings defining the ultimate locations of upper electrode regions, and initially etching in areas defined by the mask openings through the gate electrode layer at least to the gate insulating layer with minimal undercutting of the etch resist mask; introducing into the first region impurities appropriate to form a shorting region of the opposite conductivity type while employing un-etched portions of the gate electrode layer as a mask; laterally etching the previously un-etched portions of the gate electrode layer, thereby defining gate electrodes extending upwardly from and spaced along the gate insulating layer and first region principal surface; introducing into the first region between the gate electrodes impurities appropriate to form a base region of opposite conductivity type and an upper electrode region of the one conductivity type within the base region, the gate electrodes serving as masks during the introduction of impurities, and diffusing the impurities introduced to appropriately locate and configure the base and upper electrode regions such that at the principal surface the base region exists as a band of opposite conductivity type between the upper electrode region and the first region, with active portions of the band underlying at least a portion of at least one gate electrode and being separated by portions of the gate insulating layer; oxidizing at least the gate electrode sidewalls; and forming a metallized upper electrode region terminal in ohmic contact with the upper electrode and shorting regions, and forming a metallized gate terminal in ohmic contact with the gate electrode.
Claim 3
Dependent Claim
26 words
A process in accordance with claim 1, wherein the step of introducing impurities into the first region appropriate to form a shorting region comprises ion implantation.
Claim 4
Dependent Claim
37 words
A process in accordance with claim 2, wherein the ion implantation of shorting region impurities is carried out prior to removal of the gate insulating region layer, and the ion implantation is through the gate insulating layer.
Claim 5
Dependent Claim
22 words
A process in accordance with claim 1, wherein the steps of introducing base region and upper electrode region impurities comprise ion implantation.
Claim 6
Dependent Claim
35 words
A process in accordance with claim 4, wherein the steps of ion implantation are carried out prior to removal of the gate insulating region layer, and the ion implantation is through the gate insulating layer.
Claim 7
Dependent Claim
35 words
A process in accordance with claim 4, wherein at least the step of introducing base region impurities follows the step of removing the gate insulating layer between adjacent gate electrodes and comprises gas source diffusion.
Claim 8
Dependent Claim
36 words
A process in accordance with claim 4, wherein the step of introducing base region and upper region impurities follows the step of removing the gate insulating layer between adjacent gate electrodes and comprises gas source diffusion.
Claim 9
Dependent Claim
79 words
A process in accordance with claim 1, wherein: the step of preparing the wafer includes, subsequent to forming a conductive gate electrode layer, forming on the gate electrode layer a layer of a refractory metal silicide such that the refractory metal silicide forms a part of the ultimate gate electrode; and wherein during the step of oxidizing the gate electrode sidewalls, at least the exposed side surfaces of the refractory metal silicide portions of the gate electrode are oxidized.
Claim 10
Dependent Claim
21 words
A process in accordance with claim 8, wherein the steps of introducing base region and upper region impurities comprise ion implantation.
Claim 11
Dependent Claim
35 words
A process in accordance with claim 8, wherein the steps of ion implantation are carried out prior to removal of the gate insulating region layer, and the ion implantation is through the gate insulating layer.
Claim 12
Dependent Claim
35 words
A process in accordance with claim 8, wherein at least the step of introducing base region impurities follows the step of removing the gate insulating layer between adjacent gate electrodes and comprises gas source diffusion.
Claim 13
Dependent Claim
37 words
A process in accordance with claim 8, wherein the step of introducing base region and upper electrode region impurities follows the step of removing the gate insulating layer between adjacent gate electrodes and comprises gas source diffusion.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-13 | 1987-08-15 | 1988-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-13 | 1991-08-15 | 1992-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-13 | 1995-08-15 | 1996-02-14 | $7700.00 | Window Closed / Lapsed |