US4430708A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital computer for executing instructions in three time-multiplexed portions
Assignee: Unisys Corp
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Filing: 1981-05-22
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Granted: 1984-02-07
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Expires: 2001-05-22
Abstract
Abstract Disclosed is a digital computer that includes a memory means in which each of the instructions that the computer executes is represented by first, second, and third sets of microcommands. For any one particular instruction, the first set of microcommands is executed before the second set and the second set is executed before the third set. But the computer also includes a control means which directs the execution of the microcommand sets such that between the execution of the first and second microcommand sets for one instruction there is executed the third microcommand set for a prior instruction, and between the execution of the second and third microcommand sets for that same one instruction there is executed the first microcommand set for a subsequent instruction.
Inventors
- 👤 David L. Isaman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 01:58
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/28
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
211 words
A digital computer for executing sequential instructions I 1 , I 2 , . . . I N of a single program in a time-multiplexed fashion, said digital computer being comprised of: a memory means in which each of said sequential instructions is represented by respective first, second, and third sets of microcommands and where said first set of microcommands for any particular one of said sequential instructions must be executed before said second set of microcommands for that same instruction which in turn must be executed before said third set of microcommands for that same instruction; means for reading from said memory means the third set of microcommands for instruction I i-3 , the second set of microcommands for instruction I i-2 , and the first set of microcommands for instruction I i-1 , where i is an integer; and a control means for executing said third set of microcommands for instruction I i-3 , subsequently executing said second set of microcommands for instruction I i-2 , and subsequently executing said first set of microcommands for instruction I i-1 ; said means for reading and said means for executing including means for performing their respective operations in a repetitive fashion with the subscript i being incremented each time by 1.
Claim 2
Dependent Claim
211 words
A digital computer for executing sequential instructions I 1 , I 2 , . . . I N of a single program in a time-multiplexed fashion, said digital computer being comprised of: a memory means in which each of said sequential instructions is represented by respective first, second, and third sets of microcommands and where said first set of microcommands for any particular one of said sequential instructions must be executed before said second set of microcommands for that same instruction which in turn must be executed before said third set of microcommands for that same instruction; means for reading from said memory means the third set of microcommands for instruction I i-3 , the second set of microcommands for instruction I i-2 , and the first set of microcommands for instruction I i-1 , where i is an integer; and a control means for executing said third set of microcommands for instruction I i-3 , subsequently executing said second set of microcommands for instruction I i-2 , and subsequently executing said first set of microcommands for instruction I i-1 ; said means for reading and said means for executing including means for performing their respective operations in a repetitive fashion with the subscript i being incremented each time by 1.
Claim 3
Dependent Claim
100 words
A digital computer according to claim 1 and further including a stack means coupled to said control means for pushing data into the stack and popping data from the stack in response to said microcommands; said stack means being comprised of first and second portions wherein pop operations on said first stack portion are specified by microcommands in said first set, push operations on said first stack portion and pop operations on said second stack portion are specified by microcommands in said second set, and push operations on said second stack portion are specified by microcommands in said third set.
Claim 4
Dependent Claim
104 words
A digital computer according to claim 1 and further including a storage means for storing said sequential instructions, and wherein said control means is comprised of first, second, and third register means which are coupled to said storage means and are serially coupled to each other for receiving and holding portions of said instructions I i-1 , I i-2 , and I i-3 respectively, and wherein each of said register means is coupled to a respective memory means for converting the instruction in the register means to which it couples to the beginning addresses for the microcommands in a respective one of said sets.
Claim 5
Dependent Claim
97 words
A digital computer according to claim 1 and further including a storage means for storing said sequential instructions, and wherein said control means is comprised of first, second, and third register means with said first register means being coupled to said storage means and to another memory means for converting instruction I i-1 to the beginning addresses for the microcommands in said first set, and wherein said second and third register means couple through an arithmetic means to said first register means to receive therefrom the beginning addresses of the microcommands in said second and third sets.
Claim 6
Dependent Claim
39 words
A digital computer according to claim 1 wherein said memory means further includes a common set of microcommands for fetching said instructions, and wherein said control means executes said common set of microcommands as part of said iterative sequence.
Claim 7
Dependent Claim
48 words
A digital computer according to claim 1 wherein said second set of microcommands for instruction I i-2 are executed immediately after the execution of said third set of microcommands for instruction I i-3 , and said first set of microcommands for instruction I i-1 are executed immediately thereafter.
Claim 8
Dependent Claim
30 words
A digital computer according to claim 1 wherein said second instruction follows immediately after said first instruction in said program, and said third instruction follows immediately after said second instruction.
Claim 9
Dependent Claim
79 words
A digital computer according to claim 1 wherein said microcommands in said first set are different for one pair of said instructions I i-1 , I i-2 and I i-3 , said microcommands in said second set are different for another pair of said instructions I i-1 , I i-2 and I i-3 , and said microcommands in said third set are different for still another pair of said instructions I i-1 , I i-2 and I i-3 .
Claim 10
Dependent Claim
117 words
A digital computer for executing sequential instructions I 1 , I 2 , . . . I N of one program in a time-multiplexed fashion; said digital computer being comprised of: a memory means in which the ith one of said instructions I 1 , I 2 , . . . I N is represented by respective first, second, and third sets of microcommands S A i , S B i , S C i where 1≦i≦N; and a control means for executing all of said microcommand sets in the repetitive sequence S C i-3 followed by S B i-2 followed by S A i-1 starting with S A 1 and ending with S C N .
Claim 11
Dependent Claim
117 words
A digital computer for executing sequential instructions I 1 , I 2 , . . . I N of one program in a time-multiplexed fashion; said digital computer being comprised of: a memory means in which the ith one of said instructions I 1 , I 2 , . . . I N is represented by respective first, second, and third sets of microcommands S A i , S B i , S C i where 1≦i≦N; and a control means for executing all of said microcommand sets in the repetitive sequence S C i-3 followed by S B i-2 followed by S A i-1 starting with S A 1 and ending with S C N .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-06 | 1987-08-08 | 1988-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-06 | 1991-08-08 | 1992-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-06 | 1995-08-08 | 1996-02-07 | $7700.00 | Window Closed / Lapsed |