US4430624A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current mirror circuit arrangement
Assignee: Motorola Solutions Inc
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Filing: 1982-06-24
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Granted: 1984-02-07
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Expires: 2002-06-24
Abstract
Abstract A current mirror circuit arrangement wherein an output current is provided by an output transistor and coupled between the base electrode of the output transistor and a reference potential is a series combination of a resistor and a diode. Signals are fed to the base electrode of the output transistor from a voltage supply via an emitter follower circuit and a resistor is connected across the diode so as to share current with the diode to increase its impedance at low current values and consequently to improve the overall linearity of the output current input voltage characteristic.
Inventors
- 👤 Anthony D. Newton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:29
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/34; H03F3/343; H03F1/00; H03F1/32
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
122 words
A current mirror circuit arrangement comprising a transistor having a base electrode, a collector electrode for providing an output current and an emitter electrode coupled to a supply terminal; an input terminal for receiving an input signal voltage; impedance means coupled between the input terminal and the base electrode of the transistor; a series combination of resistive means and a diode coupled between the base electrode of the transistor and a supply terminal; and an impedance connected to share current with the diode such that a combination formed by the diode and the impedance is in series with the resistive means wherein the linearity of the output current/input signal voltage characteristic may be controlled in dependence upon the magnitude of said impedance.
Claim 2
Dependent Claim
122 words
A current mirror circuit arrangement comprising a transistor having a base electrode, a collector electrode for providing an output current and an emitter electrode coupled to a supply terminal; an input terminal for receiving an input signal voltage; impedance means coupled between the input terminal and the base electrode of the transistor; a series combination of resistive means and a diode coupled between the base electrode of the transistor and a supply terminal; and an impedance connected to share current with the diode such that a combination formed by the diode and the impedance is in series with the resistive means wherein the linearity of the output current/input signal voltage characteristic may be controlled in dependence upon the magnitude of said impedance.
Claim 3
Dependent Claim
18 words
A current mirror circuit arrangement as claimed in claim 1 wherein the said impedance is a current source.
Claim 4
Dependent Claim
26 words
A current mirror circuit arrangement as claimed in claim 1 wherein the said impedance is a resistor connected to pass current in parallel with the diode.
Claim 5
Dependent Claim
31 words
A current mirror circuit arrangement as claimed in claim 1 or 2 or 3 wherein the diode is formed by a transistor having its base and collector electrodes connected directly together.
Claim 6
Dependent Claim
41 words
A current mirror circuit arrangement as claimed in claim 1 wherein the impedance means includes an emitter follower transistor having a base electrode coupled to the input terminal and an emitter electrode coupled to the base electrode of the said transistor.
Claim 7
Dependent Claim
34 words
A current mirror circuit arrangement as claimed in claim 5 wherein the emitter electrode of the emitter follow transistor is coupled to the base electrode of the said transistor by means of a resistor.
Claim 8
Dependent Claim
126 words
A current mirror circuit arrangement comprising a transistor having a base electrode, a collector electrode for providing an output current and an emitter electrode; an input terminal for receiving an input signal voltage; means including first resistive means coupled between the input terminal and the base electrode of the transistor; a series combination of a diode and second resistive means coupled between the base electrode of the transistor and a supply terminal; and third resistive means connected to share current with the diode so that a combination of the diode and the third resistive means is in series with the second resistive means whereby the linearity of the output current/input signal voltage characteristic may be controlled in dependence upon the magnitude of the third resistive means.
Claim 9
Dependent Claim
126 words
A current mirror circuit arrangement comprising a transistor having a base electrode, a collector electrode for providing an output current and an emitter electrode; an input terminal for receiving an input signal voltage; means including first resistive means coupled between the input terminal and the base electrode of the transistor; a series combination of a diode and second resistive means coupled between the base electrode of the transistor and a supply terminal; and third resistive means connected to share current with the diode so that a combination of the diode and the third resistive means is in series with the second resistive means whereby the linearity of the output current/input signal voltage characteristic may be controlled in dependence upon the magnitude of the third resistive means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-06 | 1987-08-08 | 1988-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-06 | 1991-08-08 | 1992-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-06 | 1995-08-08 | 1996-02-07 | $7700.00 | Window Closed / Lapsed |