Patent US4430618A successfully refreshed from Google Patents.
US4430618A
Expired / Lapsed
US
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Input buffer circuit
Assignee: Denso Corp
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Filing: 1981-07-30
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Granted: 1984-02-07
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Expires: 2001-07-30
Abstract
Abstract In an input buffer circuit arrangement, a comparator compares a filtered input signal applied to one input with each of a first and a second reference value preset at the other input by a first setting circuit to produce a comparison output signal. According to the comparison output signal, a second setting circuit provides a third and a fourth reference value to one input of the comparator to obtain a noise-resistive characteristic.
Inventors
- 👤 Hisami Mitsueda
- 👤 Kazuyoshi Tamaki
- 👤 Hiromi Ariyoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:20
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/023; H03K3/0233; H03K3/02337; H03K3/01; H03K3/013; H03K5/00; H03K5/125; H03K5/1252
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
138 words
An input buffer circuit comprising: a filter circuit for eliminating noise included in a signal from a signal source; a voltage setting circuit for establishing a first and a second predetermined voltage; a comparator circuit for comparing an output signal of said filter circuit with each of said predetermined voltages to generate a comparison output signal; flip-flop circuit means responsive to said comparison output signal of said comparator circuit to generate a gate signal; constant current circuit means responsive to said gate signal to selectively supply a third and a fourth predetermined voltage to said comparator circuit; frequency-to-current converter means for converting said comparison output signal to a current signal corresponding to the frequency thereof; and time setting circuit means responsive to said current signal to determine a holding time of said third and fourth predetermined voltages, respectively.
Claim 2
Dependent Claim
138 words
An input buffer circuit comprising: a filter circuit for eliminating noise included in a signal from a signal source; a voltage setting circuit for establishing a first and a second predetermined voltage; a comparator circuit for comparing an output signal of said filter circuit with each of said predetermined voltages to generate a comparison output signal; flip-flop circuit means responsive to said comparison output signal of said comparator circuit to generate a gate signal; constant current circuit means responsive to said gate signal to selectively supply a third and a fourth predetermined voltage to said comparator circuit; frequency-to-current converter means for converting said comparison output signal to a current signal corresponding to the frequency thereof; and time setting circuit means responsive to said current signal to determine a holding time of said third and fourth predetermined voltages, respectively.
Claim 3
Dependent Claim
222 words
An input buffer circuit arrangement for detecting a voltage signal of electromagnetic pickup coil including a filter circuit for filtering noise components of an input signal applied thereto, first setting circuit for establishing a first and a second reference value, and a first comparator circuit for comparing the filtered output signal applied to a non-inverting terminal thereof with each of said reference values applied to an inverting terminal thereof, the improvement comprising: a first flip flop circuit responsive to the output signal of said first comparator circuit to provide a third reference signal to the non-inverting terminal of said first comparator circuit; a second flip flop circuit responsive to the inverted output signal of said first comparator circuit to provide a fourth reference signal to the inverting terminal of said first comparator circuit; a frequency-voltage converter responsive to the output of said first comparator to provide a voltage signal proportional to the frequency of output of said first comparator circuit; a voltage-current converter responsive to said frequency-voltage converter to provide a current signal proportional to the output voltage of said frequency-voltage converter; a current mirror circuit responsive to said voltage-current converter to provide a time setting signal; and a second comparator circuit responsive to said current mirror circuit to provide a reset signal to said first and second flip flop circuits, respectively.
Claim 4
Dependent Claim
222 words
An input buffer circuit arrangement for detecting a voltage signal of electromagnetic pickup coil including a filter circuit for filtering noise components of an input signal applied thereto, first setting circuit for establishing a first and a second reference value, and a first comparator circuit for comparing the filtered output signal applied to a non-inverting terminal thereof with each of said reference values applied to an inverting terminal thereof, the improvement comprising: a first flip flop circuit responsive to the output signal of said first comparator circuit to provide a third reference signal to the non-inverting terminal of said first comparator circuit; a second flip flop circuit responsive to the inverted output signal of said first comparator circuit to provide a fourth reference signal to the inverting terminal of said first comparator circuit; a frequency-voltage converter responsive to the output of said first comparator to provide a voltage signal proportional to the frequency of output of said first comparator circuit; a voltage-current converter responsive to said frequency-voltage converter to provide a current signal proportional to the output voltage of said frequency-voltage converter; a current mirror circuit responsive to said voltage-current converter to provide a time setting signal; and a second comparator circuit responsive to said current mirror circuit to provide a reset signal to said first and second flip flop circuits, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-06 | 1987-08-08 | 1988-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-06 | 1991-08-08 | 1992-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-06 | 1995-08-08 | 1996-02-07 | $7700.00 | Window Closed / Lapsed |