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Patent US4429284A successfully refreshed from Google Patents.
US4429284A
Expired / Lapsed
US
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Operational amplifier
Assignee: Intersil Corp
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Filing: 1981-11-23
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Granted: 1984-01-31
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Expires: 2001-11-23
Abstract
Abstract A differential amplifier stage is disclosed which utilizes opposed pairs of complementary transistors. The emitter electrodes of the complementary transistors of each pair are connected via matched resistors. A second matched pair of resistors are connected between the emitter electrodes of the input transistor of each complementary transistor pair. The interconnection of the second match pairs of resistors is connected to the base electrodes of the other transistors of each complementary transistor pair by a diode. A constant bias current is applied to the diode-transistor interconnection to provide current to the second pair of resistors to develop like potentials. These potentials establish floating bias potentials across the matched resistors in the emitter circuits of the complementary transistor pairs and thereby establish bias current in the transistors.
Inventors
- 👤 Carl F. Wheatley, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:13
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
266 words
A differential amplifier comprising: means for applying supply potential; first and second input terminals and an output terminal; a bias current source; first and second transistors of a first conductivity type, each having respective first and second electrodes and a principal conduction path therebetween, and respective control electrodes, the principal conduction paths being controlled by potential applied between the respective control and first electrode; respective means for connecting the second electrodes of said first and second transistor to the means for applying supply potential and for connecting the respective control electrodes to the first and second input terminals respectively; third and fourth transistors of a conductivity type complementary to said first type each having respective first and second electrodes and a principal conduction path therebetween, respective control electrodes, and potential applied between the control and first electrodes controlling the respective principal conduction paths; means for connecting the control electrodes of the third and fourth transistors to said bias current source; load means connected to the second electrodes of the third and fourth transistors and means for connecting the second electrode of the fourth transistor to said output terminal; first and second matched resistive means for respectively connecting the first electrodes of the first and third transistors, and for connecting the first electrodes of the second and fourth transistors; third and fourth matched resistive means serially connected, without intervening elements, between the first electrodes of the first and second transistors; and a single potential offset means connected between the interconnection of said third and fourth resistive means and the control electrodes of said third and fourth transistors.
Claim 2
Dependent Claim
266 words
A differential amplifier comprising: means for applying supply potential; first and second input terminals and an output terminal; a bias current source; first and second transistors of a first conductivity type, each having respective first and second electrodes and a principal conduction path therebetween, and respective control electrodes, the principal conduction paths being controlled by potential applied between the respective control and first electrode; respective means for connecting the second electrodes of said first and second transistor to the means for applying supply potential and for connecting the respective control electrodes to the first and second input terminals respectively; third and fourth transistors of a conductivity type complementary to said first type each having respective first and second electrodes and a principal conduction path therebetween, respective control electrodes, and potential applied between the control and first electrodes controlling the respective principal conduction paths; means for connecting the control electrodes of the third and fourth transistors to said bias current source; load means connected to the second electrodes of the third and fourth transistors and means for connecting the second electrode of the fourth transistor to said output terminal; first and second matched resistive means for respectively connecting the first electrodes of the first and third transistors, and for connecting the first electrodes of the second and fourth transistors; third and fourth matched resistive means serially connected, without intervening elements, between the first electrodes of the first and second transistors; and a single potential offset means connected between the interconnection of said third and fourth resistive means and the control electrodes of said third and fourth transistors.
Claim 3
Dependent Claim
29 words
The differential amplifier set forth in claim 1 wherein the potential offset means comprises a diode poled to conduct current from said bias current source in the forward direction.
Claim 4
Dependent Claim
59 words
The differential amplifier set forth in claim 1 wherein the potential offset means comprises a transistor of the same conductivity type as said third and fourth transistors having a first electrode connected to the interconnection of the third and fourth resistive means and a control and second electrode connected to the control electrodes of the third and fourth transistors.
Claim 5
Dependent Claim
46 words
The differential amplifier set forth in claims 1, 2, or 3 wherein said load means comprises a current mirror means having an input terminal connected to the second electrode of the third transistor and an output terminal connected to the second electrode of the fourth transistor.
Claim 6
Dependent Claim
19 words
The differential amplifier set forth in claim 4 wherein the first, second, third and fourth transistors comprise bipolar devices.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-01-30 | 1987-08-01 | 1988-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-01-30 | 1991-08-01 | 1992-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-01-30 | 1995-08-01 | 1996-01-31 | $7700.00 | Window Closed / Lapsed |