US4427989A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High density memory cell
Assignee: International Business Machines Corp
•
Filing: 1981-08-14
•
Granted: 1984-01-24
•
Expires: 2001-08-14
Abstract
Abstract A dynamic memory cell has a P+ injector region surrounded by an N+ region in an N- layer on an N+ layer. The injector region is placed between N+ source and drain regions. Holes injected into the N-layer are trapped by the high-low junctions at the N+, N- interfaces and are detected by sensing the source-drain current. Current levels are used to establish binary one and zero levels in the cell. Four masks in an aligned procedure simplify fabrication.
Inventors
- 👤 Narasipur G. Anantha
- 👤 Harsaran S. Bhatia
- 👤 Santosh P. Gaur
- 👤 James L. Walsh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:22
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; H; H10; H10B; H10B12/00; H10B12/10; H10B69/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
102 words
A dynamic semiconductor memory cell comprising: a substrate; a first layer of one conductivity type formed on said substrate; a second layer of one conductivity type formed on said first layer, said second layer lightly doped with respect to said first layer; an injector region formed on the surface of said second layer of a doped opposite conductivity type; a heavily doped first region of said one conductivity type surrounding said injector region within said second layer; and heavily doped second and third regions of said one conductivity type formed on the surface of said second layer defining source and drain regions.
Claim 2
Dependent Claim
102 words
A dynamic semiconductor memory cell comprising: a substrate; a first layer of one conductivity type formed on said substrate; a second layer of one conductivity type formed on said first layer, said second layer lightly doped with respect to said first layer; an injector region formed on the surface of said second layer of a doped opposite conductivity type; a heavily doped first region of said one conductivity type surrounding said injector region within said second layer; and heavily doped second and third regions of said one conductivity type formed on the surface of said second layer defining source and drain regions.
Claim 3
Dependent Claim
155 words
A dynamic storage device comprising: a substrate; a first layer of one conductivity type formed on said substrate; a second layer of one conductivity type formed on said first layer, said second layer lightly doped with respect to said first layer; deep dielectric isolation regions formed through said first and second layers and extending to said substrate defining a plurality of memory cell areas; an injector region in each memory cell area comprising a layer of a doped opposite conductivity type formed on the surface of said second layer and surrounded within said second layer by a heavily doped first region of said one conductivity type; source and drain regions in each memory cell defined by doped second and third regions of said one conductivity type formed on the surface of said second layer, and metal lines coupling respective regions in said one memory cell area to respective regions in a second memory cell area.
Claim 4
Dependent Claim
155 words
A dynamic storage device comprising: a substrate; a first layer of one conductivity type formed on said substrate; a second layer of one conductivity type formed on said first layer, said second layer lightly doped with respect to said first layer; deep dielectric isolation regions formed through said first and second layers and extending to said substrate defining a plurality of memory cell areas; an injector region in each memory cell area comprising a layer of a doped opposite conductivity type formed on the surface of said second layer and surrounded within said second layer by a heavily doped first region of said one conductivity type; source and drain regions in each memory cell defined by doped second and third regions of said one conductivity type formed on the surface of said second layer, and metal lines coupling respective regions in said one memory cell area to respective regions in a second memory cell area.
Claim 5
Independent Claim
17 words
The apparatus of claims 1 or 2 further comprising an insulating oxide coating over said second layer.
Claim 6
Independent Claim
18 words
The apparatus of claims 1 or 2 wherein said substrate comprises a layer of said opposite conductivity type.
Claim 7
Independent Claim
16 words
The apparatus of claims 1 or 2 wherein said injector region comprises a Boron P+ implant.
Claim 8
Independent Claim
18 words
The apparatus of claims 1 or 2 wherein said first, second and third regions comprise phosphorous N+ implants.
Claim 9
Independent Claim
21 words
The apparatus of claims 1 or 2 wherein said source and drain regions are on opposite sides of said injector region.
Claim 10
Independent Claim
16 words
The apparatus of claims 1 or 2 wherein said one conductivity type is N type silicon.
Claim 11
Dependent Claim
14 words
The apparatus of claim 2 wherein said memory cells comprise an N×M memory array.
Claim 12
Dependent Claim
7 words
The apparatus of claim 9 wherein N=M.
References Cited (Backward Citations)
US3868718A
Cited
US4328511A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-01-23 | 1987-07-25 | 1988-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-01-23 | 1991-07-25 | 1992-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-01-23 | 1995-07-25 | 1996-01-24 | $7700.00 | Window Closed / Lapsed |