US4426655A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory cell resistor device
Assignee: International Business Machines Corp
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Filing: 1981-08-14
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Granted: 1984-01-17
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Expires: 2001-08-14
Abstract
Abstract A dynamic memory cell uses a low barrier Schottky contact at a drain region to eliminate the need for an external gating diode. The drain is separated from source and injector regions by a heavily doped N+ reach through region extending to a heavily doped N+ blanket semiconductor. Holes injected into one of the separated regions are trapped by high-low junctions and are detected by sensing the source-drain current.
Inventors
- 👤 Harsaran S. Bhatia
- 👤 David B. Eardley
- 👤 Santosh P. Gaur
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:04
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; H; H10; H10B; H10B12/00; H10B12/10
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
135 words
A dynamic semiconductor memory cell comprising: a substrate; a first layer of one conductivity type formed on said substrate; a second layer of said one conductivity type formed on said first layer, said second layer lightly doped with respect to said first layer; means to divide said second layer into two separated areas; an injector region formed on the surface of said second layer in one of said separated areas of a doped opposite conductivity type, said injector region including a heavily doped zone of said one conductivity type surrounding said opposite conductivity type within said second layer; a source region formed in one of said two separated areas containing said injector region; and a drain region formed in the other of said separated areas by a low barrier Schottky contact with said second layer.
Claim 2
Dependent Claim
135 words
A dynamic semiconductor memory cell comprising: a substrate; a first layer of one conductivity type formed on said substrate; a second layer of said one conductivity type formed on said first layer, said second layer lightly doped with respect to said first layer; means to divide said second layer into two separated areas; an injector region formed on the surface of said second layer in one of said separated areas of a doped opposite conductivity type, said injector region including a heavily doped zone of said one conductivity type surrounding said opposite conductivity type within said second layer; a source region formed in one of said two separated areas containing said injector region; and a drain region formed in the other of said separated areas by a low barrier Schottky contact with said second layer.
Claim 3
Dependent Claim
169 words
A dynamic storage device comprising: a substrate; a first layer of one conductivity type formed on said substrate; a second layer of one conductivity type formed on said first layer, said second layer lightly doped with respect to said first layer; means to divide said second layer into two separated areas, deep dielectric isolation regions formed through said first and second layers and extending to said substrate defining a plurality of memory cell areas; an injector region in each memory cell area formed on the surface of said second layer of a doped opposite conductivity type, said injector region including a zone of heavily doped zone of said one conductivity type surrounding said opposite conductivity type within said second layer; a source region formed in each memory cell in one of said two separated areas containing said injector region; a drain region formed in each memory cell in the other of said two separated areas and comprising a low barrier Schottky contact with said second layer, and metal lines.
Claim 4
Dependent Claim
169 words
A dynamic storage device comprising: a substrate; a first layer of one conductivity type formed on said substrate; a second layer of one conductivity type formed on said first layer, said second layer lightly doped with respect to said first layer; means to divide said second layer into two separated areas, deep dielectric isolation regions formed through said first and second layers and extending to said substrate defining a plurality of memory cell areas; an injector region in each memory cell area formed on the surface of said second layer of a doped opposite conductivity type, said injector region including a zone of heavily doped zone of said one conductivity type surrounding said opposite conductivity type within said second layer; a source region formed in each memory cell in one of said two separated areas containing said injector region; a drain region formed in each memory cell in the other of said two separated areas and comprising a low barrier Schottky contact with said second layer, and metal lines.
Claim 5
Independent Claim
37 words
The apparatus of claims 1 or 2 wherein said means to divide said second layer comprises a heavily doped region of said one conductivity type extending from the surface of said second layer to said first layer.
Claim 6
Independent Claim
32 words
The apparatus of claims 1 or 2 wherein said means to divide said second layer comprises a recessed oxide insulator extending from the surface of said second layer to said first layer.
Claim 7
Independent Claim
52 words
The apparatus of claims 1 or 2 wherein said low barrier Schottky contact comprises a metal contact selected from the group consisting of titanium, tungsten, an alloy of titanium and tungsten, chromium, tantalum or other metals having a barrier height on N - type silicon of less than about 0.55 electron volt.
Claim 8
Independent Claim
16 words
The apparatus of claims 1 or 2 wherein said one conductivity type is N type silicon.
Claim 9
Independent Claim
17 words
The apparatus of claims 1 or 2 further comprising an insulating oxide coating over said second layer.
Claim 10
Independent Claim
24 words
The apparatus of claims 1 or 2 wherein said injector region comprised a boron P+ implant surrounded by a heavily doped N+ silicon zone.
Claim 11
Independent Claim
16 words
The apparatus of claims 1 or 2 wherein the resistivity of said separated areas is different.
Claim 12
Independent Claim
19 words
The apparatus of claims 1 or 2 wherein said injector region is positioned between said source and drain regions.
Claim 13
Dependent Claim
17 words
The apparatus of claim 2 wherein said memory cell areas define an array of M×N memory cells.
Claim 14
Dependent Claim
7 words
The apparatus of claim 11 wherein M=N.
References Cited (Backward Citations)
US3868718A
Cited
US4328511A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-01-16 | 1987-07-18 | 1988-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-01-16 | 1991-07-18 | 1992-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-01-16 | 1995-07-18 | 1996-01-17 | $7700.00 | Window Closed / Lapsed |