Analog quadrature signal to phase angle data conversion by a quadrature digitizer and quadrature counter

Claim 3

The apparatus according to claim 1 further including: digital-to-analog conversion means receiving said signal generated by said quadrature digitizing means and said signal generated by said quadrature up/down counting means for conversion thereof to an analog output signal representing the quadrature phase angle φ(t).

Claim 4

The apparatus according to claim 1 wherein said quadrature digitizing means includes: analog receiving means receiving S 1 (t) and S 2 (t), said analog receiving means for generating a plurality of parallel intermediate binary values; and digital outputting means receiving said plurality of parallel intermediate binary values, said digital outputting means for generating therefrom said signal indicating in binary format the fractional rotation excursions of φ(t).

Claim 5

The apparatus according to claim 1 wherein said quadrature digitizing means includes first means receiving S 1 (t) and S 2 (t), said first means for generating a plurality of first parallel intermediate binary logic levels; second means fed by said plurality of first parallel intermediate binary logic levels, said second means for generating a plurality of second parallel intermediate binary logic levels; and third means fed by said plurality of second parallel intermediate binary logic levels, said third means for outputting said signal indicating in binary format the fractional rotation excursions of φ(t).

Claim 6

The apparatus according to claim 1 wherein said quadrature digitizing means includes: first stage quadrature digitizing means receiving S 1 (t) and S 2 (t) for real time generation of a digital signal indicating in binary format the most significant bits of the fractional rotation excursions of φ(t) and for real time generation of two analog signals S 1 '(t) and S 2 '(t) representing respectively S 1 (t) and S 2 (t) minus each analog portion thereof digitized by said first stage quadrature digitizing means; and second stage quadrature digitizing means receiving S 1 '(t) and S 2 '(t) for real time generation of a digital signal indicating in binary format the least significant bits of the fractional rotation excursions of φ(t) whereby said digital signal generated by said first stage quadrature digitizing means and said digital signal generated by said second together completely indicate in binary format the fractional rotation excursions of φ(t).

Claim 7

The apparatus according to claim 5 wherein said most significant bits generated by said first stage quadrature digitizing means include in number at least three bits and wherein said least significant bits generated by said second stage quadrature digitizing means approximately equal in number the number of bits in said most significant bits generated by said first stage quadrature digitizing means.

Claim 8

The apparatus according to claim 5 wherein said first stage digitizing means includes: first means receiving S 1 (t) and S 2 (t), for generating a plurality of parallel intermediate analog signals; second means receiving S 1 (t) and S 2 (t), for generating a plurality of first parallel intermediate binary logic levels; third means fed by said plurality of first parallel intermediate binary logic levels, said third means for generating a plurality of second parallel intermediate binary logic levels; an fourth means fed by said plurality of second parallel intermediate binary logic levels, said fourth means for outputting said digital signal indicating in binary format the most significant bits of the fractional rotation excursions of φ(t); and fifth means fed by said plurality of parallel intermediate analog signals and said plurality of second parallel intermediate logic levels, said fifth means for outputting said two analog signals S 1 '(t) and S 2 '(t).

Claim 9

The apparatus according to claim 5 wherein said second stage digitizing means includes: analog receiving means receiving S 1 '(t) and S 2 '(t), for generating a plurality of parallel least significant bit intermediate binary logic levels; and digital outputting means receiving said plurality of parallel least significant bit intermediate binary logic levels, said digital outputting means for outputting said digital signal indicating in binary format the least significant bits of the fractional rotation excursions of φ(t).

Claim 10

The apparatus according to claim 7 wherein said second stage digitizing means includes: analog receiving means receiving S 1 '(t) and S 2 '(t), for generating a plurality of parallel least significant bit intermediate binary logic levels; and digital outputting means receiving said plurality of parallel least significant bit intermediate binary logic levels, said digital outputting means for outputting said digital signal indicating in binary format the least significant bits of the fractional rotation excursions of φ(t).

Claim 11

The apparatus according to claim 1 wherein said quadrature up/down counting means includes: a first analog comparator having a binary output and an input receiving thereon the quadrature signal S 1 (t); a second analog comparator having a binary output and an input receiving thereon the quadrature signal S 2 (t); a clocked D flip-flop having a D input and a Q output, said D input thereof being fed by said binary output of said first analog comparator; delay means having an input and an output for introducing a delay of period T therebetween said input thereof being fed by said Q output of said clocked D flip-flop; an exlusive OR circuit having an output, a first input fed by said Q output of said D flip-flop, and a second input fed by said output of said delay means; and an up/down counter having a clock input, an up/down mode control input, a clock enable input, and an output, said clock input fed by said output of said exclusive OR circuit, said up/down mode control fed by said output of said delay means said clock enable input fed by said binary output of said second analog comparator and said output of said up/down counter outputting said signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t).

Claim 12

The apparatus of claim 10 wherein said delay of period T of said delay means is a delay of just sufficient duration to assure reliable operation of said up/down counter.

Claim 13

The apparatus of claim 10 wherein said up/down counter. is an integrated circuit up/down counter.

Claim 14

The apparatus according to claim 1 wherein said quadrature up/down counting means includes: a first analog comparator having a binary output and an input receiving thereon the quadrature signal S 1 (t); a second analog comparator having a binary output and an input receiving thereon the quadrature signal S 2 (t); a D flip-flop having a clock, a D input, and a Q output, said D input thereof being fed by said binary output of said first analog comparator; delay means having an input and an output for introducing a delay of period T 1 therebetween, said input thereof being fed by said Q output of said clocked D flip-flop; a first exclusive OR circuit having an output, a first input fed by said Q output of said D flip-flop, and a second input fed by said output of sid delay means; a second exclusive OR circuit having an output, a first input fed by said Q output of said D flip-flop, and a second input fed by said binary output of said first analog comparator; a monostable multivibrator having a clock input, a Q output and a stable period T 2 , said clock input thereof fed by said output of said first exclusive OR circuit; an AND gate having an output connected to said clock input of said D flip-flop, a first input fed by said output of said second exclusive OR circuit, and a second input fed by said Q output of said monostable multivibrator; and an up/down counter having a clock input, an up/down mode control input, a clock enable input, and an output, said clock input fed by said output of said first exclusive OR circuit, said up/down mode control fed by said ouput of said delay means, said clock enable input fed by said binary output of said second analog comparator and said output of said up/down counter outputting said signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t).

Claim 15

The apparatus of claim 13 wherein said delay of period T 1 of said delay means is a delay of just sufficient duration to assure reliable operation of said up/down counter.

Claim 16

The apparatus of claim 14 wherein said stable period T 2 of said monostable multivibrator is a period at least equal to unity divided by the maximum reliable counting frequency of said up/down counter.

Claim 17

The apparatus of claim 13 wherein said up/down counter is an integrated circuit up/down counter.

Claim 18

The apparatus according to claim 1 wherein said quadrature up/down counting means includes: a first analog comparator having a binary output and an input receiving thereon the quadrature signal S 1 (t); a second analog comparator having a binary output and an input receiving thereon the quadrature signal S 2 (t); a logic inverter having an input fed by said binary output of said second analog comparator and a binary output for outputting the logic inverse of said binary output of said second analog comparator; and a plurality of ordered counting stages operating in parallel, each stage therein having a primary D latch circuit, a secondary D latch circuit, a primary exclusive OR circuit and a secondary exclusive OR circuit, each said primary and secondary D latch circuit having a D input, an enable input and a Q output, each said primary and secondary exclusive OR circuit having a first and a second input and an output, and within each stage; said D input of said secondary D latch circuit is coupled to said output of said secondary exclusive OR circuit, said enable input of said secondary D latch circuit is coupled to said output of said second analog comparator, said Q output of said secondary D latch circuit is coupled to said first input of said primary exclusive OR circuit, said D input of said primary D latch is coupled to said output of said primary exclusive OR circuit, said enable input of said primary D latch circuit is fed by an ANDing together of said output of said logic inverter and said Q output of said secondary D latch circuit of each preceding stage in said plurality of ordered counting stages, said Q output of said primary D latch circuit is coupled to said first input of said secondary exclusive OR circuit, said second input of both said primary and said secondary exclusive OR circuits are coupled to said output of said first analog comparator; whereby said Q output of said primary D latch circuit of each stage in said plurality of ordered counting stages provides a particularly ordered bit in said signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t).

Claim 19

A clocked quadrature up/down counting apparatus for real time generation of a signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t) of a pair of quadrature signals S 1 (t) and S 2 (t) where S 1 (t)sinφ(t) and S 2 (t)=k(t)cosφ(t) and k(t) is a signal common to the pair of quadrature signals, said apparatus comprising: a first analog comparator having a binary output and an input receiving thereon the quadrature signal S 1 (t); a second analog comparator having a binary output and an input receiving thereon the quadrature signal S 2 (t); a clocked D flip-flop having a D input and a Q output, said D input thereof being fed by said binary output of said first analog comparator; delay means having an input and an ouput for introducing a delay of period T therebetween, said input thereof being fed by said Q output of said clocked D flip-flop; an exclusive OR circuit having an output, a first input fed by said Q output of said D flip-flop, and a second input fed by said output of said delay means; and an up/down counter having a clock input, an up/down mode control input, a clock enable input, and an output, said clock input fed by said output of said exclusive OR circuit, said up/down mode control fed by said output of said delay means, said clock enable input fed by said binary output of said second analog comparator and said output of said up/down counter outputting said signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t).

Claim 20

A clocked quadrature up/down counting apparatus for real time generation of a signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t) of a pair of quadrature signals S 1 (t) and S 2 (t) where S 1 (t)sinφ(t) and S 2 (t)=k(t)cosφ(t) and k(t) is a signal common to the pair of quadrature signals, said apparatus comprising: a first analog comparator having a binary output and an input receiving thereon the quadrature signal S 1 (t); a second analog comparator having a binary output and an input receiving thereon the quadrature signal S 2 (t); a clocked D flip-flop having a D input and a Q output, said D input thereof being fed by said binary output of said first analog comparator; delay means having an input and an ouput for introducing a delay of period T therebetween, said input thereof being fed by said Q output of said clocked D flip-flop; an exclusive OR circuit having an output, a first input fed by said Q output of said D flip-flop, and a second input fed by said output of said delay means; and an up/down counter having a clock input, an up/down mode control input, a clock enable input, and an output, said clock input fed by said output of said exclusive OR circuit, said up/down mode control fed by said output of said delay means, said clock enable input fed by said binary output of said second analog comparator and said output of said up/down counter outputting said signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t).

Claim 21

The apparatus of claim 18 wherein said delay of period T of said delay means is a delay of just sufficient duration to assure reliable operation of said up/down counter.

Claim 22

The apparatus of claim 18 wherein said up/down counter is an integrated circuit up/down counter.

Claim 23

An quadrature up/down counting apparatus for real time generation of a signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t) of a pair of quadrature signals S 1 (t) and S 2 (t) where S 1 (t)=k(t)sinφ(t) and S 2 (t)=k(t)cosφ(t) and k(t) is a signal common to the pair of quadrature signals, said apparatus comprising: a first analog comparator having a binary output and an input receiving thereon the quadrature signal S 1 (t); a second analog comparator having a binary output and an input receiving thereon the quadrature signal S 2 (t); a D flip-flop having a clock input, a D input, and a Q ouput, said D input thereof being fed by said binary output of said first analog comparator; delay means having an input and an output for introducing a delay of period T 1 therebetween, said input thereof being fed by said Q output of said clocked D flip-flop; a first exclusive OR circuit having an output, a first input fed by said Q output of said D flip-flop, and a second input fed by said output of said delay means; a second exclusive OR circuit having an output, a first input fed by said Q output of said D flip-flop, and a second input fed by said binary output of said first analog comparator; a monostable multivibrator having a clock input, a Q output and a stable period T 2 , said clock input thereof fed by said output of said first exclusive OR circuit; an AND gate having an output connected to said clock input of said D flip-flop, a first input fed by said output of said second exclusive OR circuit, and a second input fed by said Q output of said monostable multivibrator; and an up/down counter having a clock input, an up/down mode control input, a clock enable input, and an output, said clock input fed by said output of said first exclusive OR circuit, said up/down mode control fed by said output of said delay means, said clock enable input fed by said binary output of said second analog comparator and said output of said up/down counter outputting said signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t).

Claim 24

An quadrature up/down counting apparatus for real time generation of a signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t) of a pair of quadrature signals S 1 (t) and S 2 (t) where S 1 (t)=k(t)sinφ(t) and S 2 (t)=k(t)cosφ(t) and k(t) is a signal common to the pair of quadrature signals, said apparatus comprising: a first analog comparator having a binary output and an input receiving thereon the quadrature signal S 1 (t); a second analog comparator having a binary output and an input receiving thereon the quadrature signal S 2 (t); a D flip-flop having a clock input, a D input, and a Q ouput, said D input thereof being fed by said binary output of said first analog comparator; delay means having an input and an output for introducing a delay of period T 1 therebetween, said input thereof being fed by said Q output of said clocked D flip-flop; a first exclusive OR circuit having an output, a first input fed by said Q output of said D flip-flop, and a second input fed by said output of said delay means; a second exclusive OR circuit having an output, a first input fed by said Q output of said D flip-flop, and a second input fed by said binary output of said first analog comparator; a monostable multivibrator having a clock input, a Q output and a stable period T 2 , said clock input thereof fed by said output of said first exclusive OR circuit; an AND gate having an output connected to said clock input of said D flip-flop, a first input fed by said output of said second exclusive OR circuit, and a second input fed by said Q output of said monostable multivibrator; and an up/down counter having a clock input, an up/down mode control input, a clock enable input, and an output, said clock input fed by said output of said first exclusive OR circuit, said up/down mode control fed by said output of said delay means, said clock enable input fed by said binary output of said second analog comparator and said output of said up/down counter outputting said signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t).

Claim 25

The apparatus of claim 21 wherein said delay of period T 1 of said delay means is a delay of just sufficient duration to assure reliable operation of said up/down counter.

Claim 26

The apparatus of claim 22 wherein said stable period T 2 of said monostable multivibrator is a period at least equal to unity divided by the maximum reliable counting frequency of said up/down counter.

Claim 27

The apparatus of claim 21 wherein said up/down counter is an integrated circuit up/down counter.

Claim 28

A synchronous quadrature up/down counting apparatus for real time generation of a signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t) of a pair of quadrature signals S 1 (t) and S 2 (t) where S 1 (t)=k(t)sinφ(t) and S 2 (t)=k(t)cosφ(t) and k(t) is a signal common to the pair of quadrature signals, said apparatus comprising: a first analog comparator having a binary output and an input receiving thereon the quadrature signal S 1 (t); a second analog comparator having a binary output and an input receiving thereon the quadrature signal S 2 (t); a logic inverter having an input fed by said binary output of said second analog comparator and a binary output for outputting the logic inverse of said binary output of said second analog comparator; and a plurality of ordered counting stages operating in parallel, each stage therein having a primary D latch circuit, a secondary D latch circuit, a primary exclusive OR circuit and a secondary exclusive OR circuit, each said primary and secondary D latch circuit having a D input, an enable input and a Q output, each said primary and secondary exclusive OR circuit having a first and second input and an output, and within each stage; said D input of said secondary D latch circuit is coupled to said output of said secondary exclusive OR circuit, said enable input of said secondary D latch circuit is coupled to said output of said second analog comparator, said Q output of said secondary D latch circuit is coupled to said first input of said primary exclusive OR circuit, said D input of said primary D latch is coupled to said output of said primary exclusive OR circuit, said enable input of said primary D latch circuit is fed by an ANDing together of said output of said logic inverter and said Q output of said secondary D latch circuit of each preceding stage in said plurality of ordered counting stages, said Q output of said primary D latch circuit is coupled to said first input of said secondary exclusive OR circuit, said second input of both said primary and said secondary exclusive OR circuits are coupled to said output of said first analog comparator; whereby said Q output of said primary D latch circuit of each stage in said plurality of ordered counting stages provides a particularly ordered bit in said signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t).

Claim 29

A synchronous quadrature up/down counting apparatus for real time generation of a signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t) of a pair of quadrature signals S 1 (t) and S 2 (t) where S 1 (t)=k(t)sinφ(t) and S 2 (t)=k(t)cosφ(t) and k(t) is a signal common to the pair of quadrature signals, said apparatus comprising: a first analog comparator having a binary output and an input receiving thereon the quadrature signal S 1 (t); a second analog comparator having a binary output and an input receiving thereon the quadrature signal S 2 (t); a logic inverter having an input fed by said binary output of said second analog comparator and a binary output for outputting the logic inverse of said binary output of said second analog comparator; and a plurality of ordered counting stages operating in parallel, each stage therein having a primary D latch circuit, a secondary D latch circuit, a primary exclusive OR circuit and a secondary exclusive OR circuit, each said primary and secondary D latch circuit having a D input, an enable input and a Q output, each said primary and secondary exclusive OR circuit having a first and second input and an output, and within each stage; said D input of said secondary D latch circuit is coupled to said output of said secondary exclusive OR circuit, said enable input of said secondary D latch circuit is coupled to said output of said second analog comparator, said Q output of said secondary D latch circuit is coupled to said first input of said primary exclusive OR circuit, said D input of said primary D latch is coupled to said output of said primary exclusive OR circuit, said enable input of said primary D latch circuit is fed by an ANDing together of said output of said logic inverter and said Q output of said secondary D latch circuit of each preceding stage in said plurality of ordered counting stages, said Q output of said primary D latch circuit is coupled to said first input of said secondary exclusive OR circuit, said second input of both said primary and said secondary exclusive OR circuits are coupled to said output of said first analog comparator; whereby said Q output of said primary D latch circuit of each stage in said plurality of ordered counting stages provides a particularly ordered bit in said signal indicating in binary format the number of full rotation excursions of the quadrature phase angle φ(t).

Claim 36

The apparatus according to claim 28 wherein said most significant bits generated by said first stage quadrature digitizing means include in number at least three bits and wherein said least significant bits generated by said second stage quadrature digitizing means approximately equal in number the number of bits in said most significant bits generated by said first stage quadrature digitizing means.

Claim 37

The apparatus according to claim 28 wherein said first stage digitizing means includes: first means receiving S 1 (t) and S 2 (t), for generating a plurality of parallel intermediate analog signals; second means receiving S 1 (t) and S 2 (t) for generating a plurality of first parallel intermediate binary logic levels; and third means fed by said plurality of first parallel intermediate binary logic levels, said third means for generating a pluarality of second parallel intermediate binary logic levels; and fourth means fed by said plurality of second parallel intermediate binary logic levels, said fourth means for outputting said digital signal indicating in binary format the most significant bits of the fractional rotation excursions of φ(t); and fifth means fed by said plurality of parallel intermediate analog signals and said plurality of second parallel intermediate logic levels, said fifth means for outputting said two analog signals S 1 '(t) and S 2 '(t).

Claim 38

The apparatus according to claim 28 wherein said second stage digitizing means includes: analog receiving means receiving S 1 '(t) and S 2 '(t), for generating a plurality of parallel least significant bit intermediate binary logic levels; and digital outputting means receiving said plurality of parallel least significant bit intermediate binary logic levels, said digital outputting means for outputting said digital signal indicating in binary format the least significant bits of the fractional rotation excursions of φ(t).