Teaching tool with RF switching

Claim 2

An rf switching apparatus for the production of digital logic electronic HIGH and LOW signals characterized as comprising: means for containing at least one rf switching apparatus within a box that is at least in part transparent to radio waves so as to form at least one rf window and wherein conventional digital logic electronic chips and discrete components may be positioned internally so as to be protected from the external environment; means for providing electrical power with a positive bus terminal and a negative bus terminal suitable for the operation of digital logic electronic chips and discrete components within the containment box; means for mounting as oscillator transistor having a base terminal, a collector terminal and an emitter terminal within the containment box; means for mounting a switching transistor having a base terminal, a collector terminal and an emitter terminal within the containment box; means for wiring a load inductor coil between the positive bus terminal and the oscillator transistor collector terminal in a manner providing spatial association between the load inductor coil and an rf window; means for wiring a variable resistor between the negative bus terminal and the oscillator transistor emitter terminal; means for wiring a coupling capacitor with a first lead to the oscillator transistor collector terminal and forming a diode node with the coupling capacitor second lead; means for wiring a first rectifier diode between the negative bus terminal and the diode node; means for wiring a first biasing resistor and a first biasing capacitor in parallel between the negative bus terminal and the oscillator transistor base terminal; means for wiring a second biasing resistor and a second biasing capacitor in parallel between the positive bus terminal and the oscillator transistor base terminal; means for wiring a time constant capacitor and a time constant resistor in parallel between the negative bus terminal and the switching transistor base terminal; means for wiring the switching transistor emitter terminal to the negative bus; means for wiring a second rectifier diode between the diode node and the switching transistor base terminal; means for wiring a load resistor between the positive bus and the switching transistor collector lead; means for wiring a digital logic signal lead to the switching transistor collector terminal; and means for placing a substance for absorbing radio frequency energy in external spatial association with the rf window and the internal load inductor coil so as to absorbingly deny feedback energy to the oscillator transistor collector terminal and thus deny the generation of electrical alternating current and thus deny the delivery of electrical direct current to the switching transistor base collector so that positive bus voltage passing through the load resistor can not pass through the switching transistor to the negative bus terminal and therefor builds up as a digital logic electronic HIGH signal on the signal lead and, when the rf absorbing substance is removed from the vicinity of the load inductor coil the feedback produces alternating current which is altered into direct current which activates the switching transistor so that positive bus voltage passing through the load resistor coil can pass through the switching transistor to the negative bus terminal and thus produce a digital logic electronic LOW signal on the signal lead.

Claim 3

An rf switching apparatus for the production of visible light signals resulting from the placement of a first rf absorbing substance and a second rf absorbing substance, characterized as comprising: a card having at least one surface suitable for the display of indicia and formed from a material transparent to radio waves in sufficient part to establish a plurality of rf window areas and having a covertly embedded first rf absorbing substance placed within at least one of such rf window areas; a decoder box with a removable top, such top formed from a material transparent to radio waves in sufficient part to establish a plurality of rf window areas and having means of guiding so that placement of the card within the guiding means aligns the card rf window areas with the top rf windows, the top also being translucent to light waves in sufficient part to establish a first light window and a second light window and the box interior having provisions for mounting components comprising; a power supply assembly wherein a plurality of storage batteries may be connected to a voltage regulator to provide a quantity of positive and negative terminals; an encodement sensor assembly having at least one covert lead wherein a plurality of modified Colpitts Oscillator circuits derive electrical power from the power supply assembly and beam rf energy through the rf windows so that, if the rf energy is absorbed by a first rf absorbing substance, a digital logic HIGH signal is produced on an associated covert output lead and, if the rf window is not shadowed by a first rf absorbing substance, a feedback of rf energy is processed so as to establish a digital logic LOW signal on the associated covert output lead and if any one of the covert output leads achieves a digital logic HIGH signal a confirmation output terminal will also establish a corresponding digital logic HIGH signal on a confirmation output lead; a response sensor assembly having at least one overt output lead wherein a plurality of modified Colpitts Oscillator circuits derive electrical power from the power supply assembly and beam rf energy through the rf windows so that, if the rf energy is absorbed by a second rf absorbing substance, a digital logic HIGH signal is produced on an associated overt output lead and, if the rf window is not shadowed by a second rf absorbing substance, a feedback of rf energy is processed so as to establish a digital logic LOW signal on the associated overt output lead; an interpretive assembly wherein a plurality of transistors derive electrical power from the power supply assembly and respond individually to received digital logic HIGH signals from associated overt output leads to power associated digital logic gates arranged to receive covert digital logic signals from associated covert output leads so that any overt powered gate receiving a covert digital logic LOW signal will establish a digital logic HIGH signal on a first light output terminal and any overt powered gate receiving a covert digital logic HIGH signal will establish a digital logic HIGH signal on a second light output terminal and if any of the plurality of first light output terminals achieves a digital logic HIGH signal a corresponding digital logic HIGH signal will be established on a first light signal output lead, and if any of the plurality of second light output terminals achieves a digital logic HIGH signal a corresponding digital logic HIGH signal will be established on a second light signal output lead; a light signal assembly wherein a first light, a second light, a confirmation transistor, a first light transistor and a second light transistor derive electrical power from the power supply assembly, the confirmation transistor is actuated by a digital logic HIGH signal from the encodement sensor assembly confirmation output lead and the first light transistor is actuated by a digital logic HIGH signal from the interpretive assembly first light signal output lead with the first light, the confirmation transistor and the first light transistor wired in series so that full circuit actuation illuminates the first light and establishes light wave radiations through the first light window of the box top, and wherein the second light transistor is actuated by a digital logic HIGH signal from the interpretive assembly second light signal output lead with the second light wired in series with the second light transistor so that full circuit actuation illuminates the second light and establishes light wave radiations through the second light window of the box top; a power control switch is connected in series between the power assembly batteries and the voltage regulator so as to allow the operational power to all of the assemblies to be selectively controlled; and a first light control switch that is connected in series between the first light and the confirmation transistor so that power to the first light can be selectively denied even though other conditions call for first light illumination.

Claim 4

An rf switching apparatus for the production of visible light signals resulting from the placement of a first rf absorbing substance and a second rf absorbing substance, characterized as comprising: a card having at least one surface suitable for the display of indicia and formed from a material transparent to radio waves in sufficient part to establish a plurality of rf window areas and having a covertly embedded first rf absorbing substance placed within at least one of such rf window areas; a decoder box with a removable top, such top formed from a material transparent to radio waves in sufficient part to establish a plurality of rf window areas and having means of guiding so that placement of the card within the guiding means aligns the card rf window areas with the top rf windows, the top also being translucent to light waves in sufficient part to establish a first light window and a second light window and the box interior having provisions for mounting components comprising; a power supply assembly wherein a plurality of storage batteries may be connected to a voltage regulator to provide a quantity of positive and negative terminals; an encodement sensor assembly having at least one covert lead wherein a plurality of modified Colpitts Oscillator circuits derive electrical power from the power supply assembly and beam rf energy through the rf windows so that, if the rf energy is absorbed by a first rf absorbing substance, a digital logic HIGH signal is produced on an associated covert output lead and, if the rf window is not shadowed by a first rf absorbing substance, a feedback of rf energy is processed so as to establish a digital logic LOW signal on the associated covert output lead and if any one of the covert output leads achieves a digital logic HIGH signal a confirmation output terminal will also establish a corresponding digital logic HIGH signal on a confirmation output lead; a response sensor assembly having at least one overt output lead wherein a plurality of modified Colpitts Oscillator circuits derive electrical power from the power supply assembly and beam rf energy through the rf windows so that, if the rf energy is absorbed by a second rf absorbing substance, a digital logic HIGH signal is produced on an associated overt output lead and, if the rf window is not shadowed by a second rf absorbing substance, a feedback of rf energy is processed so as to establish a digital logic LOW signal on the associated overt output lead; an interpretive assembly wherein a plurality of transistors derive electrical power from the power supply assembly and respond individually to received digital logic HIGH signals from associated overt output leads to power associated digital logic gates arranged to receive covert digital logic signals from associated covert output leads so that any overt powered gate receiving a covert digital logic LOW signal will establish a digital logic HIGH signal on a first light output terminal and any overt powered gate receiving a covert digital logic HIGH signal will establish a digital logic HIGH signal on a second light output terminal and if any of the plurality of first light output terminals achieves a digital logic HIGH signal a corresponding digital logic HIGH signal will be established on a first light signal output lead, and if any of the plurality of second light output terminals achieves a digital logic HIGH signal a corresponding digital logic HIGH signal will be established on a second light signal output lead; a light signal assembly wherein a first light, a second light, a confirmation transistor, a first light transistor and a second light transistor derive electrical power from the power supply assembly, the confirmation transistor is actuated by a digital logic HIGH signal from the encodement sensor assembly confirmation output lead and the first light transistor is actuated by a digital logic HIGH signal from the interpretive assembly first light signal output lead with the first light, the confirmation transistor and the first light transistor wired in series so that full circuit actuation illuminates the first light and establishes light wave radiations through the first light window of the box top, and wherein the second light transistor is actuated by a digital logic HIGH signal from the interpretive assembly second light signal output lead with the second light wired in series with the second light transistor so that full circuit actuation illuminates the second light and establishes light wave radiations through the second light window of the box top; a power control switch is connected in series between the power assembly batteries and the voltage regulator so as to allow the operational power to all of the assemblies to be selectively controlled; and a first light control switch that is connected in series between the first light and the confirmation transistor so that power to the first light can be selectively denied even though other conditions call for first light illumination.

Claim 5

The apparatus as cited in claim 2 wherein the modified Colpitts Oscillator circuits are further characterized as comprising: a positive input lead connecting to a positive bus and a negative input lead connecting to a negative bus; an oscillator transistor having a base terminal, a collector terminal and an emitter terminal; a switching transistor having a base terminal, a collector terminal and an emitter terminal; a load inductor coil connecting the positive bus terminal with the oscillator transistor collector terminal and being positioned so that developed rf energy is beamed through an associated rf window in the box top; a variable resistor connecting the negative bus terminal and the oscillator transistor emitter terminal; a coupling capacitor with a first lead connecting to the oscillator transistor collector terminal and a second lead forming a diode node; a first rectifier diode connecting the negative bus terminal and the diode node; a first biasing resistor and a first biasing capacitor forming a parallel connection between the negative bus terminal and the oscillator transistor base terminal; a second biasing resistor and a second biasing capacitor forming a parallel connection between the positive bus terminal and the oscillator transitor base terminal; a time constant capacitor and a time constant resistor forming a parallel connection between the negative bus terminal and the switching transistor base terminal; a switching jumper lead connecting the switching transistor emitter terminal and the negative bus terminal; a load resistor connecting the positive bus terminal to the switching transistor collector terminal; and a digital logic signal output lead connecting to the switching transistor collector terminal.

Claim 6

The apparatus as cited in claim 3 wherein the interpretive assembly is further characterized as comprising: a plurality of interpretive transistors, each having a base terminal, a collector terminal and an emitter terminal; a plurality of two input quad NAND chips, equal in number to the number of interpretive transistors; a positive bus lead connecting to each of the interpretive transistor collector terminals; a negative buslead connecting to each of the terminal 7 ground terminals of each of the quad NAND chips; a plurality of response sensor assembly individual covert output leads, equal in number to the number of interpretive transistors, connecting to the individual interpretive transistor base terminals; a plurality of overt jumper leads individually connecting the interpretive transistor individual emitter leads to each of the individual terminal 14 power terminals of the quad NAND chips; a plurality of encodement sensor individual covert output leads, equal in number to the number of NAND chips, connecting to each of the individual terminal 13 input terminals of the quad NAND chips; a plurality of diodic jumpers individually connecting each of the NAND chip terminals 3, 4 and 5 to each other; a plurality of passive jumpers individually connecting each of the NAND chip terminals 1, 2, 12 and 13 to each other; a first multiple diode unit, having individual input leads equal in number to the number of individual NAND chips, has individual input leads connecting to each NAND chip terminal 11 and a first signal light output lead; and a second multiple diode unit, having individual input leads equal in number to the number of individual NAND chips, has individual input leads connecting to each NAND chip terminal 6 and a second signal light output lead.

Claim 7

The apparatus as cited in claim 2, 3 or 4 wherein the power supply assembly is further characterized as comprising: a battery case containing a plurality of batteries and having a negative terminal connecting to the negative terminals of all other assemblies mounted within the containment box and a positive terminal; a power control switch penetratively mounted in a box sidewall orifice to provide external switch manipulation and, internal to the box, a power input terminal and a power output terminal; a digital logic electronic voltage regulator having a negative terminal connecting to the battery case negative terminal, an unregulated power input terminal and a regulated power output bus providing output terminals connecting to the positive terminals of all other assemblies mounted within the containment box; a switch power input lead connecting the positive terminal of the battery case to the power input terminal of the power control switch; and a switch power output lead connecting the power output terminal of the power control switch to the unregulated power input terminal of the voltage regulator.

Claim 8

The apparatus as cited in claim 2, 3 or 4 wherein the signal assembly is further characterized as comprising: a first light mounted within the decoder box in a position permitting the light, when actuated, to be beamed through the first light window in the box top and such light having an input terminal and an output terminal; a second light mounted within the decoder box in a position permitting the light, when actuated, to be beamed through the second light window in the box top and such light having an input terminal and an output terminal; a light control switch penetratively mounted in a box sidewall orifice to provide external switch manipulation and, internal to the box, a power input terminal and a power output terminal; a confirmation transistor having a base terminal, a collector terminal and an emitter terminal; a first light transistor having a base terminal, a collector terminal and an emitter terminal; a second light transistor having a base terminal, a collector terminal and an emitter terminal; a bleed resistor having an input terminal and an output terminal; means for connecting the first light output terminal to the light control switch input terminal; means for connecting the light control switch output terminal to the confirmation transistor collector terminal; means for connecting the first light input terminal and the second light input terminal in parallel to the power assembly positive bus; means for connecting the confirmation transistor emitter terminal to the first light transistor collector terminal; means for connecting the second light output terminal to the second light transistor collector terminal; means for connecting the bleed resistor between the first light transistor base terminal and emitter terminal; means for connecting the emitter terminals of the first and second light transistors in parallel to the power assembly negative bus; means for connecting the first light transistor base terminal to the interpretive assembly first light output terminal; means for connecting the second light transistor base terminal to the interpretive assembly second light output terminal; and means for connecting the confirmation transistor base terminal to the response assembly confirmation output terminal.