Connection array for interconnecting hermetic chip carriers to printed circuit boards using plated-up pillars

Claim 1

A connection array for establishing a plurality of electrical connections between circuit pads of a circuit board support and contacts of a hermetically sealed chip carrier housing wherein said contacts comprise semicircular vertical indentations in the housing horizontal edge periphery, each indentation having a conductive layer therein, comprising, in combination: a plurality of pillars extending vertically above said circuit board support in an array respectively corresponding to said indentations; said pillars being carried by different pads of said support, respectively; said pillars having horizontal dimensions to permit entry partly into said indentations and collectively to position and mechanically locate said chip carrier housing; solder between said pillars and said conductive layers establishing electrical connections therebetween free of shear stress as a result of different coefficients of expansion of the circuit board and chip carrier housing; and, said solder being visible in said indentations and externally of said pillars for inspection and cleaning.