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Patent US4422143A successfully refreshed from Google Patents.
US4422143A
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Microprocessor ALU with absolute value function
Assignee: Texas Instruments Inc
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Filing: 1980-11-24
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Granted: 1983-12-20
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Expires: 2000-11-24
Abstract
Abstract A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. The ALU circuit is constructed to modify the carry-generate term so that the twos-complement function (and others) can be generated for either of the ALU inputs. By then connecting the most significant bit of the input to the arithmetic/logic control of the ALU, the absolute value function is generated. This results in faster signed multiply and divide instructions with less circuitry.
Inventors
- 👤 Karl M. Guttag
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:50
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/503; G06F7/52; G06F7/535; G06F7/544; G06F7/57; G06F7/575; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3856; G06F2207/386; G06F2207/3872; G06F2207/535; G06F2207/5353; G06F7/499; G06F7/49905; G06F7/49926
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
197 words
An arithmetic logic unit for a microprocessor, such unit including a plurality of parallel stages, each stage comprising: a first single-bit ALU input, a second single-bit ALU input, a single-bit carry-in input from a prior one of said stages, a single-bit carry-out output to a next one of said stages, a plurality of control lines for defining an operation performed in said arithmetic logic unit, first logic means connected to receive said first and second inputs and responsive to said control lines for producing a carry propagate term output, second logic means connected to receive said first and second inputs and responsive to said control lines for producing a carry generate term output, third logic means providing an Exclusive NOR function and having first and second NOR inputs and an ALU output, the first NOR input being conditionally coupled to said carry generate term output through fourth logic means and also responsive to one of said control lines, the second NOR input being coupled to said carry propagate term output, and said fourth logic means coupled to said first NOR input and to said carry generate term output being responsive to one other of said control lines.
Claim 2
Dependent Claim
197 words
An arithmetic logic unit for a microprocessor, such unit including a plurality of parallel stages, each stage comprising: a first single-bit ALU input, a second single-bit ALU input, a single-bit carry-in input from a prior one of said stages, a single-bit carry-out output to a next one of said stages, a plurality of control lines for defining an operation performed in said arithmetic logic unit, first logic means connected to receive said first and second inputs and responsive to said control lines for producing a carry propagate term output, second logic means connected to receive said first and second inputs and responsive to said control lines for producing a carry generate term output, third logic means providing an Exclusive NOR function and having first and second NOR inputs and an ALU output, the first NOR input being conditionally coupled to said carry generate term output through fourth logic means and also responsive to one of said control lines, the second NOR input being coupled to said carry propagate term output, and said fourth logic means coupled to said first NOR input and to said carry generate term output being responsive to one other of said control lines.
Claim 3
Dependent Claim
27 words
A unit according to claim 1 wherein said first and second logic means both receive true and a complement inputs from said first and second ALU inputs.
Claim 4
Dependent Claim
20 words
A unit according to claim 2 wherein said first NOR input of said third logic means receives said carry-in input.
Claim 5
Dependent Claim
43 words
A unit according to claim 1 wherein said arithmetic logic unit contains a plurality of like bits parallel stages, each having said first and second ALU inputs connected to receive respective parallel bits from parallel bus means, to process data bits in parallel.
Claim 6
Dependent Claim
73 words
A unit according to claim 3 wherein said fourth logic means includes: a first transistor connecting said first NOR input to a reference level to hold such first NOR input unconditionally in one logic state when a one of said control inputs is in one state, or to couple said first NOR input to said carry-in input and carry generate term output when said one of the control inputs is in another state.
Claim 7
Dependent Claim
58 words
A unit according to claim 5 wherein said fourth logic means also includes: a second transistor having source-to-drain path in series between said carry-in input and said carry-out output with a gate coupled to said carry propagate term output, and transistor means conditionally coupling said carry-out output to a reference level in response to said carry-generate term output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-19 | 1987-06-20 | 1987-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-19 | 1991-06-20 | 1991-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-19 | 1995-06-20 | 1995-12-20 | $7700.00 | Window Closed / Lapsed |